View STA369BWSTR_8175365.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this is information on a product in full production. september 2014 docid016861 rev 7 1/92 sta369bws 2.1-channel 40-watt high-efficiency digital audio system sound terminal ? datasheet - production data features ? wide-range supply voltage, 4.5 v to 21.5 v ? three power output configurations: ? 2 channels of ternary pwm (2 x 20 w into 8 ? at 18 v) + pwm output ? 2 channels of ternary pwm (2 x 20 w into 8 ? at 18 v) + ternary stereo line-out ? 2.1 channels of binary pwm (left, right, lfe) (2 x 9 w into 4 ?? +1 x 20 w into 8 ? at 18 v) ? ffx with 100-db snr and dynamic range ? scalable ffx modulation index (up to 100%) ? selectable 32- to 192-khz input sample rates ? i 2 c control with selectable device address ? digital gain/attenuation +48 db to -80 db with 0.125-db/step resolution ? soft volume update with programmable ratio ? individual channel and master gain/attenuation ? two independent drcs configurable as a dual-band anti-clipper (b 2 drc) or as independent limiters/compressors with optional global drc capability ? eq-drc for drc based on filtered signals ? dedicated lfe processing for bass boosting with 0.125-db/step resolution ? audio presets: ? 15 preset crossover filters ? 5 preset anti-clipping modes ? preset night-time listening mode ? individual channel soft/hard mute ? independent channel volume and dsp bypass ? i 2 s input data interface ? input and output channel mapping ? automatic invalid input-detect mute ? up to 8 user-programmable biquads/channel ? three coefficients banks for eq presets storing with fast recall via i 2 c interface ? extended filter dynamics +4/-4 for better sound shaping and easier filter implementation ? bass/treble tones and de-emphasis control ? selectable high-pass filter for dc blocking ? advanced am interference frequency switching and noise suppression modes ? f3x? advanced pwm modulation scheme for carrier suppression (headphone or line output) ? selectable high- or low-bandwidth noise-shaping topologies ? selectable clock input ratio ? 96-khz internal processing sample rate with quantization error noise shaping for very low cut-off frequency filters ? thermal overload and short-circuit protection embedded ? video apps: 576 x f s input mode supported ? pcb manufacturing short-circuit protection technology powersso-36 with exposed pad down (epd) table 1. device summary order code package packaging sta369bws powersso-36 epd tube STA369BWSTR powersso-36 epd tape and reel www.st.com
contents sta369bws 2/92 docid016861 rev 7 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 electrical specifications for the digital section . . . . . . . . . . . . . . . . . . . . . 14 3.5 electrical specifications for the power section . . . . . . . . . . . . . . . . . . . . . 15 3.6 power on/off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 serial audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.0.1 timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.0.2 delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.0.3 channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 processing data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6i 2 c bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1.1 data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1.2 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1.3 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1.4 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.3.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.3.2 multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4.1 current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
docid016861 rev 7 3/92 sta369bws contents 92 6.4.2 current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4.3 random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4.4 random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 configuration registers (addr 0x00 to 0x05) . . . . . . . . . . . . . . . . . . . . . . . 27 7.1.1 configuration register a (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.1.2 configuration register b (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1.3 configuration register c (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.1.4 configuration register d (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1.5 configuration register e (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.1.6 configuration register f (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2 volume control registers (addr 0x06 - 0x0a) . . . . . . . . . . . . . . . . . . . . . . 46 7.2.1 mute/line output configuration register (addr 0x06) . . . . . . . . . . . . . . . . 47 7.2.2 master volume register (addr 0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.2.3 channel 1 volume (addr 0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.2.4 channel 2 volume (addr 0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.2.5 channel 3 / line output volume (addr 0x0a) . . . . . . . . . . . . . . . . . . . . . 48 7.3 audio preset registers (addr 0x0b and 0x0c) . . . . . . . . . . . . . . . . . . . . . 49 7.3.1 audio preset register 1 (addr 0x0b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.3.2 audio preset register 2 (addr 0x0c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.4 channel configuration registers (addr 0x0e - 0x10) . . . . . . . . . . . . . . . . . 51 7.5 tone control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.6 dynamic control registers (addr 0x12 - 0x15) . . . . . . . . . . . . . . . . . . . . . 53 7.6.1 limiter 1 attack/release rate (addr 0x12) . . . . . . . . . . . . . . . . . . . . . . . . 53 7.6.2 limiter 1 attack/release threshold (addr 0x13) . . . . . . . . . . . . . . . . . . . 53 7.6.3 limiter 2 attack/release rate (addr 0x14) . . . . . . . . . . . . . . . . . . . . . . . . 54 7.6.4 limiter 2 attack/release threshold (addr 0x15) . . . . . . . . . . . . . . . . . . . 54 7.6.5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.6.6 limiter 1 extended attack threshold (addr 0x32) . . . . . . . . . . . . . . . . . . 58 7.6.7 limiter 1 extended release threshold (addr 0x33) . . . . . . . . . . . . . . . . . 59 7.6.8 limiter 2 extended attack threshold (addr 0x34) . . . . . . . . . . . . . . . . . . 59 7.6.9 limiter 2 extended release threshold (addr 0x35) . . . . . . . . . . . . . . . . . 59 7.7 user-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . . 59 7.7.1 coefficient address register (addr 0x16) . . . . . . . . . . . . . . . . . . . . . . . . 59 7.7.2 coefficient b1 data register bits (addr 0x17 - 0x19) . . . . . . . . . . . . . . . . 59
contents sta369bws 4/92 docid016861 rev 7 7.7.3 coefficient b2 data register bits (addr 0x1a - 0x1c) . . . . . . . . . . . . . . . 60 7.7.4 coefficient a1 data register bits (addr 0x1d - 0x1f) . . . . . . . . . . . . . . . 60 7.7.5 coefficient a2 data register bits (addr 0x20 - 0x22) . . . . . . . . . . . . . . . . 60 7.7.6 coefficient b0 data register bits (addr 0x23 - 0x25) . . . . . . . . . . . . . . . . 61 7.7.7 coefficient read/write control register (addr 0x26) . . . . . . . . . . . . . . . . . 61 7.7.8 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.8 variable max power correction registers (addr 0x27 - 0x28) . . . . . . . . . . 66 7.9 distortion compensation registers (addr 0x29 - 0x2a) . . . . . . . . . . . . . . . 66 7.10 fault detect recovery constant registers (addr 0x2b - 0x2c) . . . . . . . . . . 66 7.11 device status register (addr 0x2d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.12 eq coefficients and drc configuration register (addr 0x31) . . . . . . . . . . 68 7.13 extended configuration register (addr 0x36) . . . . . . . . . . . . . . . . . . . . . . 69 7.13.1 dual-band drc (b 2 drc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.13.2 eq drc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.14 soft volume configuration registers (addr 0x37 - 0x38) . . . . . . . . . . . . . . 72 7.15 drc rms filter coefficients (addr 0x39-0x3e) . . . . . . . . . . . . . . . . . . . . . 73 7.16 extra volume resolution configuration registers (addr 0x3f) . . . . . . . . . . 74 7.17 short-circuit protection mode registers shok (addr 0x46) . . . . . . . . . . . 75 7.18 quantization error noise correction (addr 0x48) . . . . . . . . . . . . . . . . . . . . 76 7.19 extended coefficient range up to +4/-4 (addr 0x49, 0x4a) . . . . . . . . . . . . 77 7.20 miscellaneous registers (addr 0x4b, 0x4c) . . . . . . . . . . . . . . . . . . . . . . . 78 7.20.1 misc1 (addr 0x4b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.20.2 misc2 (addr 0x4c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.21 global drc after b2drc (gdrc) bit (addr 0x4d, bit d0) . . . . . . . . . . . . 81 7.22 bad pwm detection registers (addr 0x4d, 0x4e, 0x4f) . . . . . . . . . . . . . . 82 7.23 coefficient ram crc protection (addr 0x60-0x6c) . . . . . . . . . . . . . . . . . 82 7.23.1 bqchke registers (addr 0x60 - 0x62) . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.23.2 xcchke registers (addr 0x63 - 0x65) . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.23.3 bqchkr registers (addr 0x66 - 0x68) . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.23.4 xcchkr registers (addr 0x69 - 0x6b) . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.23.5 chkctrl register (addr 0x6c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.23.6 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.1 application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
docid016861 rev 7 5/92 sta369bws contents 92 8.2 pll filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.3 typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
list of tables sta369bws 6/92 docid016861 rev 7 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5. recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 6. electrical specifications - digital section (t amb = 25 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7. electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 table 8. timing parameters for slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 9. register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 10. master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 11. input sampling rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 12. internal interpolation ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 13. ir bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 14. thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 table 15. thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 16. fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 17. serial audio input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 18. serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 19. support serial audio input formats for msb-first (saifb = 0) . . . . . . . . . . . . . . . . . . . . . . . 30 table 20. supported serial audio input formats for lsb-first (saifb = 1) . . . . . . . . . . . . . . . . . . . . . 30 table 21. delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 22. channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 23. ffx power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 24. ffx compensating pulse size bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 25. compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 26. overcurrent warning bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 27. high-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 28. de-emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 29. dsp bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 30. postscale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 31. biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 32. dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 33. zero-detect mute enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 34. submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 35. max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 36. max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 37. noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 38. am mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 39. pwm speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 40. distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 41. zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 42. soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 43. output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 44. output configuration engine selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 45. invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 46. binary output mode clock loss detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 47. lrck double trigger protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 48. auto eapd on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
docid016861 rev 7 7/92 sta369bws list of tables 92 table 49. ic power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 50. external amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 51. line output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 52. master volume offset as a function of mvol[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 53. channel volume as a function of cxvol[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 54. audio preset gain compression/limiters selection for amgc[3:2] = 00. . . . . . . . . . . . . . . . 49 table 55. am interference frequency switching bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 56. audio preset am switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 57. bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 58. bass management crossover frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 59. tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 60. eq bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 61. volume bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 62. binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 63. channel limiter mapping as a function of cxls bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 64. channel output mapping as a function of cxom bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 65. tone control boost/cut as a function of btc and ttc bits . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 66. limiter attack rate vs lxa bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 67. limiter release rate vs lxr bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 68. limiter attack threshold vs lxat bits (ac mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 69. limiter release threshold vs lxrt bits (ac mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 70. limiter attack threshold vs lxat bits (drc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 71. limiter release threshold vs lxrt bits (drc mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 72. ram block for biquads, mixing, scaling, bass management. . . . . . . . . . . . . . . . . . . . . . . . 63 table 73. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 74. eq ram select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 75. anti clipping and drc preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 76. anti-clipping selection for amgc[3:2] = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 77. bit ps48db description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 78. bit xar1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 79. bit xar2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 80. bit bq5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 81. bit bq6 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 82. bit bq7 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 83. bit svupe description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 84. bit svdwe description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 85. bits cxvr description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 86. bits vresen and vrestg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 87. coefficients extended range configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 88. f3x bits configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 89. external amplifier enabler configuration bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 90. pndlsl bits configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 91. powersso-36 epd dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 92. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
list figures sta369bws 8/92 docid016861 rev 7 list figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. pin connection powersso-36 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3. test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 4. power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5. power-off sequence for pop-free turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. timing diagram for sai interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 7. left and right processing, section 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 8. left and right processing, section 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 9. write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 10. read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 11. ocfg = 00 (default value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 12. ocfg = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 13. ocfg = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 14. ocfg = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 15. output mapping scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 16. 2.0 channels (ocfg = 00) pwm slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 17. 2.1 channels (ocfg = 01) pwm slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 18. 2.1 channels (ocfg = 10) pwm slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 19. basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 20. b 2 drc scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 21. eqdrc scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 22. application circuit for 2 or 2.1-channel configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 23. application circuit for mono btl configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 24. output configuration for stereo btl mode (r l = 8 ?? . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 25. powersso-36 power derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 26. powersso-36 epd outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
docid016861 rev 7 9/92 sta369bws description 92 1 description the sta369bws is an integrated solution of digital audio processing, digital amplifier controls and power output stage to create a high-power single-chip ffx digital amplifier with high-quality and high-efficiency. three channels of ffx processing are provided. the ffx processor implements the ternary, binary and binary differential processing capabilities of the full ffx processor. the sta369bws is part of the sound terminal ? family that provides full digital audio streaming to the speakers and offers cost effectiveness, low power dissipation and sound enrichment. the power section consists of four independent half-bridges. these can be configured via digital control to operate in different modes. for example, 2.1 channels can be provided by two half-bridges and a single full-bridge, supplying up to 2 x 9 w + 1 x 20 w of output power or two channels can be provided by two full-bridges, supplying up to 2 x 20 w of output power. the ic can also be configured as 2.1 channels with 2 x 20 w supplied by the device plus a drive for an external ffx power amplifier, such as sta533wf or sta515w. one other option is to configure the ic as having one channel output that can be provided by parallel btl to obtain 1 x 40 w of output power. in this configuration the config pin must be connected to vdd. also provided in the sta369bws are a full assortment of digital processing features. this includes up to 8 programmable biquads (eq) per channel. special digital signal processing techniques are available to manage low-frequency quantization noise in filters with very low cut-off frequencies. the coefficient range -4 to +4 allows easy high-shelf filter usage and better sound shaping. available presets enable a time-to-market advantage by substantially reducing the amount of software development needed for functions such as audio preset volume loudness, preset volume curves and preset eq settings. there are also new advanced am radio interference reduction modes. dual-band drc dynamically equalizes the system to provide linear frequency speaker response regardless of output power level. this feature separates the audio frequency band into two sub-bands independently processed to provide better sound clarity and to avoid speaker saturation. the serial audio data input interface accepts all possible formats, including the popular i 2 s format. the high-quality conversion from pcm audio to ffx pwm switching provides over 100 db of snr and of dynamic range. the new f3x? modulation is capable of digitally filtering the pwm carrier to simplify external filtering requirements, am interference and emi. f3x? is implemented in the auxiliary output of sta369bws and it is specifically designed for application where a simple op-amp can be used to drive an auxiliary headphone line.
description sta369bws 10/92 docid016861 rev 7 figure 1. block diagram protection current/thermal logic regulators bias power control ffx pll volume control channel 1a channel 1b channel 2a channel 2b i 2 s interface power digital dsp i 2 c
docid016861 rev 7 11/92 sta369bws pin connections 92 2 pin connections 2.1 connection diagram figure 2. pin connection powersso-36 (top view) 2.2 pin description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 vdd_dig gnd_dig scl sda int_line reset sdi lrcki bicki xti gnd_pll filter_pll vdd_pll pwrdn gnd_dig vdd_dig twarn / out4a eapd / out4b gnd_sub sa test_mode vss vcc_reg out2b gnd2 vcc2 out2a out1b vcc1 gnd1 out1a gnd_reg vdd config out3b / ffx3b out3a / ffx3a ep, exposed pad (device ground) table 2. pin description pin type name description 1 gnd gnd_sub substrate ground 2 i sa i 2 c select address (pull-down) 3 i test_mode this pin must be connected to ground (pull-down) 4 i/o vss internal reference at v cc - 3.3 v 5 i/o vcc_reg internal v cc reference 6 o out2b output half-bridge channel 2b 7 gnd gnd2 power negative supply 8 power vcc2 power positive supply 9 o out2a output half-bridge channel 2a 10 o out1b output half-bridge channel 1b
pin connections sta369bws 12/92 docid016861 rev 7 11 power vcc1 power positive supply 12 gnd gnd1 power negative supply 13 o out1a output half-bridge channel 1a 14 gnd gnd_reg internal ground reference 15 power vdd internal 3.3 v reference voltage 16 i config parallel mode command 17 o out3b / ffx3b pwm out channel 3b / external bridge driver 18 o out3a / ffx3a pwm out channel 3a / external bridge driver 19 o eapd / out4b power down for external bridge / pwm out channel 4b 20 i/o twarn / out4a thermal warning from external bridge (pull-up when input) / pwm out channel 4a 21 power vdd_dig digital supply voltage 22 gnd gnd_dig digital ground 23 i pwrdn power down (pull-up) 24 power vdd_pll positive supply for pll 25 i filter_pll connection to pll filter 26 gnd gnd_pll negative supply for pll 27 i xti pll input clock 28 i bicki i 2 s serial clock 29 i lrcki i 2 s left/right clock 30 i sdi i 2 s serial data channels 1 and 2 31 i reset reset (pull-up) 32 o int_line fault interrupt 33 i/o sda i 2 c serial data 34 i scl i 2 c serial clock 35 gnd gnd_dig digital ground 36 power vdd_dig digital supply voltage - - ep exposed pad for pcb heatsink, to be connected to gnd table 2. pin description (continued) pin type name description
docid016861 rev 7 13/92 sta369bws electrical specifications 92 3 electrical specifications 3.1 absolute maximum ratings warning: stresses beyond those listed in table 3 above may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditions? are not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. in the real application, power supplies with nominal values rated within the recommended operating conditions, may experience some rising beyond the maximum operating conditions for a short time when no or very low current is sinked (amplifier in mute state). in this case the reliability of the device is guaranteed, provided that the absolute maximum ratings are not exceeded. 3.2 thermal data table 3. absolute maximum ratings symbol parameter min typ max unit v cc power supply voltage (pins vccx) -0.3 - 24 v v dd digital supply voltage (pins vdd_dig) -0.3 - 4.0 v v dd pll supply voltage (pin vdd_pll) -0.3 - 4.0 v t op operating junction temperature -20 - 150 c t stg storage temperature -40 - 150 c table 4. thermal data symbol parameter min typ max unit r th j-case thermal resistance junction-case (thermal pad) - - 1.5 c/w t th-sdj thermal shut-down junction temperature - 150 - c t th-w thermal warning temperature - 130 - c t th-sdh thermal shut-down hysteresis - 20 - c r th j-amb thermal resistance junction-ambient (1) 1. see chapter 9: package thermal characteristics on page 88 for details. - 24 - c/w
electrical specifications sta369bws 14/92 docid016861 rev 7 3.3 recommended operating conditions 3.4 electrical specifications for the digital section table 5. recommended operating condition symbol parameter min typ max unit v cc power supply voltage (vccxa, vccxb) 4.5 - 21.5 v v dd_dig digital supply voltage 2.7 3.3 3.6 v v dd_pll pll supply voltage 2.7 3.3 3.6 v t amb ambient temperature -20 - 70 c table 6. electrical specifications - digital section (t amb = 25 c) symbol parameter conditions min typ max unit i il low level input current without pull-up/down device vi = 0 v - - 1 a i ih high level input current without pull-up/down device vi = vdd_dig = 3.6 v --1 a v il low level input voltage - - - 0.2 * vdd_dig v v ih high level input voltage - 0.8 * vdd_dig --v v ol low level output voltage iol = 2 ma - 0.4 * vdd_dig v v oh high level output voltage ioh = 2 ma 0.8 * vdd_dig --v r pu equivalent pull-up/down resistance --50-k ?
docid016861 rev 7 15/92 sta369bws electrical specifications 92 3.5 electrical specifications for the power section the specifications given in this section are valid for the operating conditions: v cc = 18 v, f = 1 khz, f sw = 384 khz, t amb = 25 c and r l = 8 ? , unless otherwise specified. table 7. electrical specifications - power section symbol parameter conditions min typ max unit po output power btl thd = 1% - 16 - w thd = 10% - 20 - output power se thd = 1%,r l = 4 ? -7- w thd = 10%,r l = 4 ? -9- r dson power p-channel or n-channel mosfet l d = 0.75 a - - 250 m ?? gp power p-channel rdson matching l d = 0.75 a - 100 - % gn power n-channel rdson matching l d = 0.75 a - 100 - % idss power p-channel/n-channel leakage v cc = 20 v - - 1 ? a t r rise time resistive load, see figure 3 below - - 10 ns t f fall time - - 10 ns i vcc supply current from v cc in power down pwrdn = 0 - 0.3 - ? a supply current from v cc in operation pwrdn = 1 - 15 - ma i vdd supply current ffx processing internal clock = 49.152 mhz - 55 - ma i lim overcurrent limit (1) 2.5 3.0 - a i scp short -circuit protection r l = 0 ? 3.0 3.6 - a v uvp undervoltage protection - - - 4.3 v t min output minimum pulse width no load 20 40 60 ns dr dynamic range - - 100 - db snr signal to noise ratio, ternary mode a-weighted - 100 - db signal to noise ratio binary mode - - 90 - db thd+n total harmonic distortion + noise ffx stereo mode, po = 1 w f = 1 khz - 0.2 - % x talk crosstalk ffx stereo mode, <5 khz one channel driven at 1 w, other channel measured -80-db ? peak efficiency, ffx mode po = 2 x 20 w into 8 ?? -90- % peak efficiency, binary modes po = 2 x 9 w into 4 ? + 1 x 20 w into 8 ? -87- 1. limit the current if overcurrent warning detect adjustment bypass is enabled (register bit confc.ocrb on page 33 ). when disabled refer to i scp .
electrical specifications sta369bws 16/92 docid016861 rev 7 figure 3. test circuit dtr dtf vcc (3/4)vcc (1/2)vcc (1/4)vcc t outxy low current dead time = max(dtr, dtf) +vcc duty cycle = 50% inxy outxy gnd vdc = vcc/2 rload = 8 ? + -
docid016861 rev 7 17/92 sta369bws electrical specifications 92 3.6 power on/off sequence figure 4. power-on sequence note: the definition of a stable clock is when f max - f min < 1 mhz. section : serial data interface on page 29 gives information on setting up the i 2 s interface. figure 5. power-off sequence for pop-free turn-off note: no specific vcc and vdd_dig turn ? on sequence is required tr = minimum time between xti master clock stable and reset removal: 1 ms tc = minimum time between reset removal and i 2 c program, sequence start: 1ms note: no specific vcc and vdd_dig turn ? off sequence is required
serial audio interface sta369bws 18/92 docid016861 rev 7 4 serial audio interface the sta369bws audio serial input interface was designed to interface with standard digital audio components and to accept a number of serial data formats. the sta369bws always acts as the slave when receiving audio input from standard digital audio components. serial data for two channels is provided using three inputs: left/right clock lrcki, serial clock bicki, and serial data sdi12. the sai bit and the saifb bit are used to specify the serial data format. the default serial data format is i 2 s, msb-first. 4.0.1 timings in the sta369bws the bicki and lrcki pins are configured as inputs and they must be supplied by the external peripheral. figure 6. timing diagram for sai interface 4.0.2 delay serial clock enable to tolerate anomalies in some i 2 s master devices, a pll clock cycle delay can be added to the bicki signal before the sai interface. 4.0.3 channel input mapping each channel received via i 2 s can be mapped to any internal processing channel via the channel input mapping registers. this allows for flexibility in processing. the default settings of these registers map each i 2 s input channel to its corresponding processing channel. table 8. timing parameters for slave mode symbol parameter min typ max unit t bcy bick cycle time 80 - - ns t bch bick pulse width high 40 - - ns t bcl bick pulse width low 40 - - ns t lrsu lrcki setup time to bicki strobing edge 40 - - ns t lrh lrcki hold time to bicki strobing edge 40 - - ns t lrjt lrcki jitter tolerance 40 ns
docid016861 rev 7 19/92 sta369bws processing data paths 92 5 processing data paths figure 7 and figure 8 below show the data processing paths inside sta369bws. the whole processing chain is composed of two consecutive sections. in the first one, dual-channel processing is implemented and in the second section each channel is fed into the post-mixing block either to generate a third channel (typically used in 2.1 output configuration and with crossover filters enabled) or to have the channels processed by the dual-band drc block (2.0 output configuration with crossover filters used to define the cut-off frequency of the two bands). the first section, figure 7 , begins with a 2x oversampling fir filter providing 2 * f s audio processing. then a selectable high-pass filter removes the dc level (enabled if hpb = 0). the left and right channel processing paths can include up to 8 filters, depending on the selected configuration (bits bql, bq5, bq6, bq7 and xo[3:0]). by default, four user programmable, independent filters per channel are enabled, plus the preconfigured de-emphasis, bass and treble controls (bql = 0, bq5 = 0, bq6 = 0, bq7 = 0). if the coefficient sets for the two channels are linked (bql = 1) it is possible to use the de-emphasis, bass and treble filters in a user defined configuration (provided the relevant bqx bits are set). in this case both channels use the same processing coefficients and can have up to seven filters each. if bql = 0 the bqx bits are ignored and the fifth, sixth and seventh filters are configured as de-emphasis, bass and treble controls, respectively. figure 7. left and right processing, section 1 moreover, the common 8th filter can be available on both channels provided the predefined crossover frequencies are not used, xo[3:0] = 0, and the dual-band drc is not used. in the second section, figure 8 , mixing and crossover filters are available. if b 2 drc is not enabled they are fully user-programmable and allow the generation of a third channel (2.1 outputs). alternatively, in mode b 2 drc, these blocks are used to split the sub-band and define the cut-off frequencies of the two bands. a prescaler and a final postscaler allow full control over the signal dynamics before and after the filtering stages. a mixer function is also available.
processing data paths sta369bws 20/92 docid016861 rev 7 in all the available configurations high-pass filtering with a 2-hz cut-off frequency is applied before the postscale block. this filter cannot be disabled. figure 8. left and right processing, section 2 dual-band drc enabled dual-band drc disabled #8 #8
docid016861 rev 7 21/92 sta369bws i 2 c bus specification 92 6 i 2 c bus specification the sta369bws supports the i 2 c protocol via the input ports scl and sda_in (master to slave) and the output port sda_out (slave to master). this protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. the device that controls the data transfer is known as the master and the other as the slave. the master always starts the transfer and provides the serial clock for synchronization. the sta369bws is always a slave device in all of its communications. it supports up to 400 kb/s (fast-mode bit rate). for correct operation of the i 2 c interface ensure that the master clock generated by the pll has a frequency at least 10 times higher than the frequency of the applied scl clock. 6.1 communication protocol 6.1.1 data transition or change data changes on the sda line must only occur when the clock scl is low. a sda transition while the clock is high is used to identify a start or stop condition. 6.1.2 start condition start is identified by a high to low transition of the data bus, sda, while the clock, scl, is stable in the high state. a start condition must precede any command for data transfer. 6.1.3 stop condition stop is identified by low to high transition of sda while scl is stable in the high state. a stop condition terminates communication between sta369bws and the bus master. 6.1.4 data input during the data input the sta369bws samples the sda signal on the rising edge of scl. for correct device operation the sda signal must be stable during the rising edge of the clock and the data can change only when the scl line is low. 6.2 device addressing to start communication between the master and the sta369bws, the master must initiate with a start condition. following this, the master sends onto the sda line 8-bits (msb first) corresponding to the device select address and read or write mode bit. the seven most significant bits are the device address identifiers, corresponding to the i 2 c bus definition. in the sta369bws the i 2 c interface has two device addresses depending on the sa pin configuration, 0x38 when sa = 0, and 0x3a when sa = 1. the eighth bit (lsb) identifies a read or write operation (r/w); this is set to 1 for read and to 0 for write. after a start condition the sta369bws identifies the device address on the sda bus and if a match is found, acknowledges the identification during the 9th bit time frame. the byte following the device identification is the address of a device register.
i 2 c bus specification sta369bws 22/92 docid016861 rev 7 6.3 write operation following the start condition the master sends a device select code with the rw bit set to 0. the sta369bws acknowledges this and then waits for the byte of internal address. after receiving the internal byte address the sta369bws again responds with an acknowledgement. 6.3.1 byte write in the byte write mode the master sends one data byte, this is acknowledged by the sta369bws. the master then terminates the transfer by generating a stop condition. 6.3.2 multi-byte write the multi-byte write modes can start from any internal address. the master generating a stop condition terminates the transfer. figure 9. write mode sequence 6.4 read operation 6.4.1 current address byte read following the start condition the master sends a device select code with the rw bit set to 1. the sta369bws acknowledges this and then responds by sending one byte of data. the master then terminates the transfer by generating a stop condition. 6.4.2 current address multi-byte read the multi-byte read modes can start from any internal address. sequential data bytes are read from sequential addresses within the sta369bws. the master acknowledges each data byte read and then generates a stop condition terminating the transfer. 6.4.3 random address byte read following the start condition the master sends a device select code with the rw bit set to 0. the sta369bws acknowledges this and then the master writes the internal address byte. after receiving, the internal byte address the sta369bws again responds with an acknowledgement. the master then initiates another start condition and sends the device select code with the rw bit set to 1. the sta369bws acknowledges this and then responds by sending one byte of data. the master then terminates the transfer by generating a stop condition.
docid016861 rev 7 23/92 sta369bws i 2 c bus specification 92 6.4.4 random address multi-byte read the multi-byte read modes could start from any internal address. sequential data bytes are read from sequential addresses within the sta369bws. the master acknowledges each data byte read and then generates a stop condition terminating the transfer. figure 10. read mode sequence
register description sta369bws 24/92 docid016861 rev 7 7 register description note: addresses exceeding the maximum address number must not be written. table 9. register summary addr name d7 d6 d5 d4 d3 d2 d1 d0 0x00 confa fdrb twab twrb ir1 ir0 mcs2 mcs1 mcs0 0x01 confb c2im c1im dscke saifb sai3 sai2 sai1 sai0 0x02 confc ocrb reserved csz3 csz2 csz1 csz0 om1 om0 0x03 confd sme zde drc bql psl dspb demp hpb 0x04 confe sve zce dccv pwms ame nsbw mpc mpcv 0x05 conff eapd pwdn ecle ldte bcle ide ocfg1 ocfg0 0x06 muteloc loc1 loc0 reserved reserved c3m c2m c1m reserved 0x07 mvol mvol[7:0] 0x08 c1vol c1vol[7:0] 0x09 c2vol c2vol[7:0] 0x0a c3vol c3vol[7:0] 0x0b auto1 reserved reserved amgc[1:0] reserved reserved reserved reserved 0x0c auto2 xo3 xo2 xo1 xo0 amam2 amam1 amam0 amame 0x0d auto3 reserved 0x0e c1cfg c1om1 c1om0 c1ls1 c1ls0 c1bo c1vbp c1eqbp c1tcb 0x0f c2cfg c2om1 c2om0 c2ls1 c2ls0 c2bo c2vbp c2eqbp c2tcb 0x10 c3cfg c3om1 c3om0 c3ls1 c3ls0 c3bo c3vbp reserved reserved 0x11 tone ttc3 ttc2 ttc1 ttc0 btc3 btc2 btc1 btc0 0x12 l1ar l1a3 l1a2 l1a1 l1a0 l1r3 l1r2 l1r1 l1r0 0x13 l1atrt l1at3 l1at2 l1at1 l1at0 l1rt3 l1rt2 l1rt1 l1rt0 0x14 l2ar l2a3 l2a2 l2a1 l2a0 l2r3 l2r2 l2r1 l2r0 0x15 l2atrt l2at3 l2at2 l2at1 l2at0 l2rt3 l2rt2 l2rt1 l2rt0 0x16 cfaddr reserved reserved cfa[5:0] 0x17 b1cf1 c1b[23:16] 0x18 b1cf2 c1b[15:8] 0x19 b1cf3 c1b[7:0] 0x1a b2cf1 c2b[23:16] 0x1b b2cf2 c2b[15:8] 0x1c b2cf3 c2b[7:0] 0x1d a1cf1 c3b[23:16] 0x1e a1cf2 c3b[15:8]
docid016861 rev 7 25/92 sta369bws register description 92 0x1f a1cf3 c3b[7:0] 0x20 a2cf1 c4b[23:16] 0x21 a2cf2 c4b[15:8] 0x22 a2cf3 c4b[7:0] 0x23 b0cf1 c5b[23:16] 0x24 b0cf2 c5b[15:8] 0x25 b0cf3 c5b[7:0] 0x26 cfud reserved ra r1 wa w1 0x27 mpcc1 mpcc[15:8] 0x28 mpcc2 mpcc[7:0] 0x29 dcc1 dcc[15:8] 0x2a dcc2 dcc[7:0] 0x2b fdrc1 fdrc[15:8] 0x2c fdrc2 fdrc[7:0] 0x2d status pllul fault uvfault reserved ocfault ocwarn tfault twarn 0x2e reserved reserved 0x2f reserved reserved 0x30 reserved reserved 0x31 eqcfg xob reserved reserved amgc[3:2] reserved sel[1:0] 0x32 eath1 eathen1 eath1[6:0] 0x33 erth1 erthen1 erth1[6:0] 0x34 eath2 eathen2 eath2[6:0] 0x35 erth2 erthen2 erth2[6:0] 0x36 confx mdrc[1:0] ps48db xar1 xar2 bq5 bq6 bq7 0x37 svca reserved reserved svupe svup[4:0] 0x38 svcb reserved reserved svdwe svdw[4:0] 0x39 rms0a r_c0[23:16] 0x3a rms0b r_c0[15:8] 0x3b rms0c r_c0[7:0] 0x3c rms1a r_c1[23:16] 0x3d rms1b r_c1[15:8] 0x3e rms1c r_c1[7:0] 0x3f evolres vresen vrestg c3vr[1:0] c2vr[1:0] c1vr[1:0] 0x40 reserved reserved 0x41 reserved reserved table 9. register summary (continued) addr name d7 d6 d5 d4 d3 d2 d1 d0
register description sta369bws 26/92 docid016861 rev 7 0x42 reserved reserved 0x43 reserved reserved 0x44 reserved reserved 0x45 reserved reserved 0x46 shok gnd1a gnd1b gnd2a gnd2b vcc1a vcc1b vcc2a vcc2b 0x47 reserved reserved 0x48 nshape nshxen nshb7en nshb6en nshb5en nshb4en nshb3en nshb2en nshb1en 0x49 cxtb4b1 cxtb4[1:0] cxtb3[1:0] cxtb2[1:0] cxtb1[1:0] 0x4a cxtb7b5 reserved reserved cxtb7[1:0] cxtb6[1:0] cxtb5[1:0] 0x4b misc1 rpdnen nshhpen bridgoff f3xen[1:0] cpwmen reserved boost 0x4c misc2 lpdp lpd lpde pndlsl[2:0] reserved shen 0x4d bpth bpth[5:0] reserved gdrc 0x4e badpwm bp4b bp4a bp3b bp3a bp2b bp2a bp1b bp1a 0x4f bptim bptim[7:0] 0x50 reserved reserved 0x51 reserved reserved 0x52 reserved reserved 0x53 reserved reserved 0x54 reserved reserved 0x55 reserved reserved 0x56 reserved reserved 0x60 bqchke0 bqchke[7:0] 0x61 bqchke1 bqchke[15:8] 0x62 bqchke2 bqchke[23:16] 0x63 xcchke0 xcchke[7:0] 0x64 xcchke1 xcchke[15:8] 0x65 xcchke2 xcchke[23:16] 0x66 bqchkr0 bqchkr[7:0] 0x67 bqchkr1 bqchkr[15:8] 0x68 bqchkr2 bqchkr[23:16] 0x69 xcchkr0 xcchkr[7:0] 0x6a xcchkr1 xcchkr[15:8] 0x6b xcchkr2 xcchkr[23:16] 0x6c chkctrl xcauto xcres xccmp xcgo bcauto bcres bccmp bcgo table 9. register summary (continued) addr name d7 d6 d5 d4 d3 d2 d1 d0
docid016861 rev 7 27/92 sta369bws register description 92 7.1 configuration registers (addr 0x00 to 0x05) 7.1.1 configuration register a (addr 0x00) master clock select the sta369bws supports sample rates of 32 khz, 44.1 khz, 48 khz, 88.2 khz, 96 khz, 176.4 khz, and 192 khz. therefore the internal clock is: ? 32.768 mhz for 32 khz ? 45.1584 mhz for 44.1 khz, 88.2 khz, and 176.4 khz ? 49.152 mhz for 48 khz, 96 khz, and 192 khz the external clock frequency provided to the xti pin must be a multiple of the input sample frequency (f s ). the relationship between the input clock and the input sample rate is determined by both the mcsx and the ir (input rate) register bits. the mcsx bits determine the pll factor generating the internal clock and the ir bit determines the oversampling ratio used internally. interpolation ratio select d7 d6 d5 d4 d3 d2 d1 d0 fdrb twab twrb ir1 ir0 mcs2 mcs1 mcs0 01100011 table 10. master clock select bit r/w rst name description 0 r/w 1 mcs0 selects the ratio between the input i 2 s sample frequency and the input clock. 1 r/w 1 mcs1 2 r/w 0 mcs2 table 11. input sampling rates input sample rate fs (khz) ir mcs [2:0] 101 100 011 010 001 000 32, 44.1, 48 00 576 * fs 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs 88.2, 96 01 na 64 * fs 128 * fs 192 * fs 256 * fs 384 * fs 176.4, 192 1x na 32 * fs 64 * fs 96 * fs 128 * fs 192 * fs table 12. internal interpolation ratio bit r/w rst name description 4:3 r/w 00 ir [1:0] selects internal interpolation ratio based on input i 2 s sample frequency
register description sta369bws 28/92 docid016861 rev 7 the sta369bws has variable interpolation (oversampling) settings such that internal processing and ffx output rates remain consistent. the first processing block interpolates by either 2-times or 1-time (pass-through) or provides a 2-times downsample. the oversampling ratio of this interpolation is determined by the ir bits. thermal warning recovery bypass this bit sets the behavior of the ic after a thermal warning disappears. if twrb is enabled the device automatically restores the normal gain and output limiting is no longer active. if it is disabled the device keeps the output limit active until a reset is asserted or until twrb set to 0. this bit works in conjunction with twab thermal warning adjustment bypass bit twab enables automatic output limiting when a power stage thermal warning condition persists for longer than 400ms. when the feature is active (twab = 0) the desired output limiting, set through bit twocl (-3 db by default) at address 0x37 in the ram coefficients bank, is applied. the way the limiting acts after the warning condition disappears is controlled by bit twrb. table 13. ir bit settings as a function of input sample rate input sample rate fs (khz) ir 1st stage interpolation ratio 32 00 2-times oversampling 44.1 00 2-times oversampling 48 00 2-times oversampling 88.2 01 pass-through 96 01 pass-through 176.4 10 2-times downsampling 192 10 2-times downsampling table 14. thermal warning recovery bypass bit r/w rst name description 5 r/w 1 twrb 0: thermal warning recovery enabled 1: thermal warning recovery disabled table 15. thermal warning adjustment bypass bit r/w rst name description 6 r/w 1 twab 0: thermal warning adjustment enabled 1: thermal warning adjustment disabled
docid016861 rev 7 29/92 sta369bws register description 92 fault detect recovery bypass the on-chip power block provides feedback to the digital controller which is used to indicate a fault condition (either overcurrent or thermal). when fault is asserted the power control block attempts a recovery from the fault by asserting the 3-state output, holding it for period of time in the range of 0.1 ms to 1 second, as defined by the fault-detect recovery constant register (fdrc registers 0x2b-0x2c), then toggling it back to normal condition. this sequence is repeated as long as the fault indication exists. this feature is enabled by default but can be bypassed by setting the fdrb control bit to 1. the fault condition is also asserted by a low-state pulse of the normally high int_line output pin. 7.1.2 configuration register b (addr 0x01) serial audio input interface format serial data interface the sta369bws audio serial input interfaces with standard digital audio components and accepts a number of serial data formats. sta369bws always acts as slave when receiving audio input from standard digital audio components. serial data for two channels is provided using three inputs: left/right clock lrcki, serial clock bicki, and serial data sdi. bits sai and bit saifb are used to specify the serial data format. the default serial data format is i 2 s, msb first. available formats are shown in the tables and figure that follow. serial data first bit table 16. fault detect recovery bypass bit r/w rst name description 7 r/w 0 fdrb 0: fault detect recovery enabled 1: fault detect recovery disabled d7 d6 d5 d4 d3 d2 d1 d0 c2im c1im dscke saifb sai3 sai2 sai1 sai0 10000000 table 17. serial audio input interface bit r/w rst name description 0 r/w 0 sai0 determines the interface format of the input serial digital audio interface. 1 r/w 0 sai1 2 r/w 0 sai2 3 r/w 0 sai3 table 18. serial data first bit saifb format 0 msb-first 1 lsb-first
register description sta369bws 30/92 docid016861 rev 7 table 19. support serial audio input formats for msb-first (saifb = 0) bicki sai [3:0] saifb interface format 32 * fs 0000 0 i 2 s 15-bit data 0001 0 left/right-justified 16-bit data 48 * fs 0000 0 i 2 s 16 to 23-bit data 0001 0 left-justified 16 to 24-bit data 0010 0 right-justified 24-bit data 0110 0 right-justified 20-bit data 1010 0 right-justified 18-bit data 1110 0 right-justified 16-bit data 64 * fs 0000 0 i 2 s 16 to 24-bit data 0001 0 left-justified 16 to 24-bit data 0010 0 right-justified 24-bit data 0110 0 right-justified 20-bit data 1010 0 right-justified 18-bit data 1110 0 right-justified 16-bit data table 20. supported serial audio input formats for lsb-first (saifb = 1) bicki sai [3:0] saifb interface format 32 * fs 1100 1 i 2 s 15-bit data 1110 1 left/right-justified 16-bit data 48 * fs 0100 1 i 2 s 23-bit data 0100 1 i 2 s 20-bit data 1000 1 i 2 s 18-bit data 1100 1 lsb first i 2 s 16-bit data 0001 1 left-justified 24-bit data 0101 1 left-justified 20-bit data 1001 1 left-justified 18-bit data 1101 1 left-justified 16-bit data 0010 1 right-justified 24-bit data 0110 1 right-justified 20-bit data 1010 1 right-justified 18-bit data 1110 1 right-justified 16-bit data
docid016861 rev 7 31/92 sta369bws register description 92 to make the sta369bws work properly, the serial audio interface lrcki clock must be synchronous to the pll output clock. it means that: ? n-4< = (frequency of pll clock) / (frequency of lrcki) = < n+4 cycles, where n depends on the settings in table 13 on page 28 . ? the pll must be locked. if these two conditions are not met, and ide bit (register 0x05, bit 2) is set to 1, the sta369bws immediately mutes the i 2 s pcm data out (provided to the processing block) and it freezes any active processing task. clock desyncronization can happen during sta369bws operation because of source switching or tv channel change. to avoid audio side effects, like click or pop noise, it is strongly recommended to complete the following actions: 1. soft volume change 2. i 2 c read /write instructions while the serial audio interface and the internal pll are still synchronous. delay serial clock enable 64 * fs 0000 1 i 2 s 24-bit data 0100 1 i 2 s 20-bit data 1000 1 i 2 s 18-bit data 1100 1 lsb first i 2 s 16-bit data 0001 1 left-justified 24-bit data 0101 1 left-justified 20-bit data 1001 1 left-justified 18-bit data 1101 1 left-justified 16-bit data 0010 1 right-justified 24-bit data 0110 1 right-justified 20-bit data 1010 1 right-justified 18-bit data 1110 1 right-justified 16-bit data table 21. delay serial clock enable bit r/w rst name description 5 r/w 0 dscke 0: no serial clock delay 1: serial clock delay by 1 core clock cycle to tolerate anomalies in some i 2 s master devices table 20. supported serial audio input formats for lsb-first (saifb = 1) (continued) bicki sai [3:0] saifb interface format
register description sta369bws 32/92 docid016861 rev 7 channel input mapping each channel received via i 2 s can be mapped to any internal processing channel via the channel input mapping registers. this allows for flexibility in processing. the default settings of these registers maps each i 2 s input channel to its corresponding processing channel. 7.1.3 configuration register c (addr 0x02) ffx power output mode the ffx power output mode selects how the ffx output timing is configured. different power devices use different output modes. ffx compensating pulse size register table 22. channel input mapping bit r/w rst name description 6 r/w 0 c1im 0: processing channel 1 receives left i 2 s input 1: processing channel 1 receives right i 2 s input 7 r/w 1 c2im 0: processing channel 2 receives left i 2 s input 1: processing channel 2 receives right i 2 s input d7 d6 d5 d4 d3 d2 d1 d0 ocrb reserved csz3 csz2 csz1 csz0 om1 om0 10010111 table 23. ffx power output mode bit r/w rst name description 0 r/w 1 om0 selects configuration of ffx output: 00: drop compensation 01: discrete output stage: tapered compensation 10: full-power mode 11: variable drop compensation (cszx bits) 1 r/w 1 om1 table 24. ffx compensating pulse size bits bit r/w rst name description 2 r/w 1 csz0 when om[1,0] = 11, this register determines the size of the ffx compensating pulse from 0 clock ticks to 15 clock periods. 3 r/w 1 csz1 4 r/w 1 csz2 5 r/w 0 csz3
docid016861 rev 7 33/92 sta369bws register description 92 overcurrent warning adjustment bypass the ocrb is used to indicate how sta369bws behaves when an overcurrent warning condition occurs. if ocrb = 0 and the overcurrent condition happens, the power control block forces an adjustment to the modulation limit (default is -3 db) in an attempt to eliminate the overcurrent warning condition. once the overcurrent warning clipping adjustment is applied, it remains in this state until reset is applied or ocrb is set to 1. the level of adjustment can be changed via the twocl (thermal warning/overcurrent limit) setting at address 0x37 of the user defined coefficient ram ( section 7.7.7 on page 61 ). the ocrb can be enabled while the output bridge is already on. 7.1.4 configuration register d (addr 0x03) high-pass filter bypass the sta369bws features an internal digital high-pass filter for the purpose of ac coupling. the purpose of this filter is to prevent dc signals from passing through a ffx amplifier. dc signals can cause speaker damage. when hpb = 0, this filter is enabled. table 25. compensating pulse size csz[3:0] compensating pulse size 0000 0 ns (0 tick) compensating pulse size 0001 20 ns (1 tick) clock period compensating pulse size ?? 1111 300 ns (15 tick) clock period compensating pulse size table 26. overcurrent warning bypass bit r/w rst name description 7 r/w 1 ocrb 0: overcurrent warning adjustment enabled 1: overcurrent warning adjustment disabled d7 d6 d5 d4 d3 d2 d1 d0 sme zde drc bql psl dspb demp hpb 01000000 table 27. high-pass filter bypass bit r/w rst name description 0 r/w 0 hpb 1: bypass internal ac coupling digital high-pass filter
register description sta369bws 34/92 docid016861 rev 7 de-emphasis dsp bypass setting the dspb bit bypasses the eq function of the sta369bws. postscale link postscale functionality can be used for power-supply error correction. for multi-channel applications running off the same power-supply, the postscale values can be linked to the value of channel 1 for ease of use and update the values faster. biquad coefficient link for ease of use, all channels can use the biquad coefficients loaded into the channel-1 coefficient ram space by setting the bql bit to 1. therefore, any eq updates only have to be performed once. dynamic range compression/anti-clipping bit table 28. de-emphasis bit r/w rst name description 1 r/w 0 demp 0: no de-emphasis 1: enable de-emphasis on all channels table 29. dsp bypass bit r/w rst name description 2 r/w 0 dspb 0: normal operation 1: bypass of biquad and bass/treble functions table 30. postscale link bit r/w rst name description 3 r/w 0 psl 0: each channel uses individual postscale value 1: each channel uses channel 1 postscale value table 31. biquad coefficient link bit r/w rst name description 4 r/w 0 bql 0: each channel uses coefficient values 1: each channel uses channel 1 coefficient values table 32. dynamic range compression/anti-clipping bit bit r/w rst name description 5 r/w 0 drc 0: limiters act in anti-clipping mode 1: limiters act in dynamic range compression mode
docid016861 rev 7 35/92 sta369bws register description 92 both limiters can be used in one of two ways, anti-clipping or dynamic range compression. when used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. in dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level. zero-detect mute enable setting the zde bit enables the zero-detect automatic mute. the zero-detect circuit looks at the data for each processing channel at the output of the crossover (bass management) filter. if any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled. submix mode enable 7.1.5 configuration register e (addr 0x04) max power correction variable max power correction table 33. zero-detect mute enable bit r/w rst name description 6 r/w 1 zde 0: automatic zero-detect mute disabled 1: automatic zero-detect mute enabled table 34. submix mode enable bit r/w rst name description 7 r/w 0 sme 0: submix into left/right disabled 1: submix into left/right enabled d7 d6 d5 d4 d3 d2 d1 d0 sve zce dccv pwms ame nsbw mpc mpcv 11000010 table 35. max power correction variable bit r/w rst name description 0 r/w 0 mpcv 0: use standard mpc coefficient 1: use mpcc bits for mpc coefficient table 36. max power correction bit r/w rst name description 1 r/w 1 mpc 0: function disabled 1: enables power bridge correction for thd reduction near maximum power output.
register description sta369bws 36/92 docid016861 rev 7 setting the mpc bit turns on special processing that corrects the sta369bws power device at high power. this mode should lower the thd+n of a full ffx system at maximum power output and slightly below. if enabled, mpc is operational in all output modes except tapered (om[1,0] = 01) and binary. when ocfg = 00, mpc has no effect on channels 3 and 4, the line-out channels. noise-shaper bandwidth selection am mode enable sta369bws features a ffx processing mode that minimizes the amount of noise generated in frequency range of am radio. this mode is intended for use when ffx is operating in a device with an am tuner active. the snr of the ffx processing is reduced to approximately 83 db in this mode, which is still greater than the snr of am radio. pwm speed mode distortion compensation variable enable table 37. noise-shaper bandwidth selection bit r/w rst name description 2 r/w 0 nsbw 1: third-order ns 0: fourth-order ns table 38. am mode enable bit r/w rst name description 3 r/w 0 ame 0: normal ffx operation. 1: am reduction mode ffx operation table 39. pwm speed mode bit r/w rst name description 4 r/w 0 pwms 0: normal speed (384 khz) all channels 1: odd speed (341.3 khz) all channels table 40. distortion compensation variable enable bit r/w rst name description 5 r/w 0 dccv 0: use preset dc coefficient 1: use dcc coefficient
docid016861 rev 7 37/92 sta369bws register description 92 zero-crossing volume enable the zce bit enables zero-crossing volume adjustments. when volume is adjusted on digital zero-crossings no clicks are audible. soft volume update enable 7.1.6 configuration register f (addr 0x05) output configuration table 41. zero-crossing volume enable bit r/w rst name description 6 r/w 1 zce 1: volume adjustments only occur at digital zero- crossings 0: volume adjustments occur immediately table 42. soft volume update enable bit r/w rst name description 7 r/w 1 sve 1: volume adjustments ramp according to svup/svdw settings 0: volume adjustments occur immediately d7 d6 d5 d4 d3 d2 d1 d0 eapd pwdn ecle ldte bcle ide ocfg1 ocfg0 01011100 table 43. output configuration bit r/w rst name description 0 r/w 0 ocfg0 selects the output configuration 1 r/w 0 ocfg1
register description sta369bws 38/92 docid016861 rev 7 note: to the left of the arrow is the processing channel. when using channel output mapping, any of the three processing channel outputs can be used for any of the three inputs. figure 11. ocfg = 00 (default value) table 44. output configuration engine selection ocfg[1:0] output configuration config pin 00 2 channel (full-bridge) power, 2 channel data-out: 1a/1b ? 1a/1b 2a/2b ? 2a/2b lineout1 ? 3a/3b lineout2 ? 4a/4b line out configuration determined by loc register 0 01 2 (half-bridge), 1(full-bridge) on-board power: 1a ? 1a binary 0 2a ? 1b binary 90 3a/3b ? 2a/2b binary 45 1a/b ? 3a/b binary 0 2a/b ? 4a/b binary 90 0 10 2 channel (full-bridge) power, 1 channel ffx: 1a/1b ? 1a/1b 2a/2b ? 2a/2b 3a/3b ? 3a/3b eapdext and twarnext active 0 11 1 channel mono-parallel: 3a ? 1a/1b w/ c3bo 45 3b ? 2a/2b w/ c3bo 45 1a/1b ? 3a/3b 2a/2b ? 4a/4b 1
docid016861 rev 7 39/92 sta369bws register description 92 figure 12. ocfg = 01 figure 13. ocfg = 10 figure 14. ocfg = 11 the sta369bws can be configured to support different output configurations. for each pwm output channel a pwm slot is defined. a pwm slot is always 1 / (8 * fs) seconds length. the pwm slot define the maximum extension for pwm rise and fall edge, that is, rising edge as far as the falling edge cannot range outside pwm slot boundaries.
register description sta369bws 40/92 docid016861 rev 7 figure 15. output mapping scheme for each configuration the pwm signals from the digital driver are mapped in different ways to the power stage:
docid016861 rev 7 41/92 sta369bws register description 92 2.0 channels, two full-bridges (ocfg = 00) mapping: ? ffx1a -> out1a ? ffx1b -> out1b ? ffx2a -> out2a ? ffx2b -> out2b ? ffx3a -> out3a ? ffx3b -> out3b ? ffx4a -> out4a ? ffx4b -> out4b default modulation: ? ffx1a/1b configured as ternary ? ffx2a/2b configured as ternary ? ffx3a/3b configured as lineout ternary ? ffx4a/4b configured as lineout ternary on channel 3 line out (loc bits = 00) the same data as channel 1 processing is sent. on channel 4 line out (loc bits = 00) the same data as channel 2 processing is sent. in this configuration, volume control or eq have no effect on channels 3 and 4. in this configuration the pwm slot phase is the following as shown in figure 16 . figure 16. 2.0 channels (ocfg = 00) pwm slots
register description sta369bws 42/92 docid016861 rev 7 2.1 channels, two half-bridges + one full-bridge (ocfg = 01) mapping: ? ffx1a -> out1a ? ffx2a -> out1b ? ffx3a -> out2a ? ffx3b -> out2b ? ffx1a -> out3a ? ffx1b -> out3b ? ffx2a -> out4a ? ffx2b -> out4b modulation: ? ffx1a/1b configured as binary ? ffx2a/2b configured as binary ? ffx3a/3b configured as binary ? ffx4a/4b configured as binary in this configuration, channel 3 has full control (volume, eq, etc?). on out3/out4 channels the channel 1 and channel 2 pwm are replicated. in this configuration the pwm slot phase is the following as shown in figure 17 . figure 17. 2.1 channels (ocfg = 01) pwm slots
docid016861 rev 7 43/92 sta369bws register description 92 2.1 channels, two full-bridges + one external full-bridge (ocfg = 10) mapping: ? ffx1a -> out1a ? ffx1b -> out1b ? ffx2a -> out2a ? ffx2b -> out2b ? ffx3a -> out3a ? ffx3b -> out3b ? eapd -> out4a ? twarn -> out4b default modulation: ? ffx1a/1b configured as ternary ? ffx2a/2b configured as ternary ? ffx3a/3b configured as ternary ? ffx4a/4b is not used in this configuration, channel 3 has full control (volume, eq, etc?). on out4 channel the external bridge control signals are muxed. in this configuration the pwm slot phase is the following as shown in figure 18 . figure 18. 2.1 channels (ocfg = 10) pwm slots
register description sta369bws 44/92 docid016861 rev 7 1 channel mono-parallel (ocfg = 11) mapping: ffx1a -> out3a ffx1b -> out3b ffx2a -> out4a ffx2b -> out4b ffx3a -> out1a/out1b ffx3b -> out2a/out2b in this configuration, the config pin must be connected to the vdd pin.
docid016861 rev 7 45/92 sta369bws register description 92 invalid input detect mute enable setting the ide bit enables this function, which looks at the input i 2 s data and automatically mutes if the signals are perceived as invalid. binary output mode clock loss detection detects loss of input mclk in binary mode and will output 50% duty cycle. lrck double trigger protection ldte, when enabled, prevents double trigger of lrclk on instable i2s input. auto eapd on clock loss when active, issues a power device power down signal (eapd) on clock loss detection. ic power down table 45. invalid input detect mute enable bit r/w rst name description 2 r/w 1 ide 0: disables the automatic invalid input detect mute 1: enables the automatic invalid input detect mute table 46. binary output mode clock loss detection bit r/w rst name description 3 r/w 1 bcle 0: binary output mode clock loss detection disabled 1: binary output mode clock loss detection enable table 47. lrck double trigger protection bit r/w rst name description 4 r/w 1 ldte 0: lrclk double trigger protection disabled 1: lrclk double trigger protection enabled table 48. auto eapd on clock loss bit r/w rst name description 5 r/w 0 ecle 0: auto eapd on clock loss not enabled 1: auto eapd on clock loss table 49. ic power down bit r/w rst name description 6 r/w 1 pwdn 0: ic power down low-power condition 1: ic normal operation
register description sta369bws 46/92 docid016861 rev 7 the pwdn register is used to place the ic in a low-power state. when pwdn is written as 0, the output begins a soft-mute. after the mute condition is reached, eapd is asserted to power down the power-stage, then the master clock to all internal hardware expect the i 2 c block is gated. this places the ic in a very low power consumption state. external amplifier power down the eapd register directly disables/enables the internal power circuitry. when eapd = 0, the internal power section is placed in a low-power state (disabled). this register also controls the ffx4b / eapd output pin when ocfg = 10. 7.2 volume control registers (addr 0x06 - 0x0a) the volume structure of the sta369bws consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. the individual channel volumes are adjustable in 0.5 db steps from +48 db to -80 db. as an example if c3vol = 0x00 or +48 db and mvol = 0x18 or -12 db, then the total gain for channel 3 = +36 db. the channel mutes provide a ?soft mute? with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (approximately 96 khz). a ?hard (instantaneous) mute? can be obtained by programming a value of 0xff (255) in any channel volume register. when volume offsets are provided via the master volume register any channel whose total volume is less than -80 db is muted. all changes in volume take place at zero-crossings when zce = 1 ( configuration register e (addr 0x04) on page 35 ) on a per channel basis as this creates the smoothest possible volume transitions. when zce = 0, volume updates occur immediately. table 50. external amplifier power down bit r/w rst name description 7 r/w 0 eapd 0: external power stage power down active 1: normal operation
docid016861 rev 7 47/92 sta369bws register description 92 7.2.1 mute/line output configuration register (addr 0x06) line output is only active when ocfg = 00. in this case loc determines the line output configuration. the source of the line output is always the channel 1 and 2 inputs. 7.2.2 master volume register (addr 0x07) 7.2.3 channel 1 volume (addr 0x08) 7.2.4 channel 2 volume (addr 0x09) d7 d6 d5 d4 d3 d2 d1 d0 loc1 loc0 reserved reserved c3m c2m c1m reserved 00000000 table 51. line output configuration loc[1:0] line output configuration 00 line output fixed - no volume, no eq 01 line output variable - channel 3 volume effects line output, no eq 10 line output variable with eq - channel 3 volume effects line output d7 d6 d5 d4 d3 d2 d1 d0 mvol7 mvol6 mvol5 mvol4 mvol3 mvol2 mvol1 mvol0 11111111 table 52. master volume offset as a function of mvol[7:0] mvol[7:0] volume offset from channel value 00000000 (0x00) 0 db 00000001 (0x01) -0.5 db 00000010 (0x02) -1 db ?? 01001100 (0x4c) -38 db ?? 11111110 (0xfe) -127.5 db 11111111 (0xff) default mute, not to be used during operation d7 d6 d5 d4 d3 d2 d1 d0 c1vol7 c1vol6 c1vol5 c1vol4 c1vol3 c1vol2 c1vol1 c1vol0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c2vol7 c2vol6 c2vol5 c2vol4 c2vol3 c2vol2 c2vol1 c2vol0 01100000
register description sta369bws 48/92 docid016861 rev 7 7.2.5 channel 3 / line output volume (addr 0x0a) d7 d6 d5 d4 d3 d2 d1 d0 c3vol7 c3vol6 c3vol5 c3vol4 c3vol3 c3vol2 c3vol1 c3vol0 01100000 table 53. channel volume as a function of cxvol[7:0] cxvol[7:0] volume 00000000 (0x00) +48 db 00000001 (0x01) +47.5 db 00000010 (0x02) +47 db ?? 0101 1111 (0x5f) +0.5 db 01100000 (0x60) 0 db 01100001 (0x61) -0.5 db ?? 11010111 (0xd7) -59.5 db 11011000 (0xd8) -60 db 11011001 (0xd9) -61 db 11011010 (0xda) -62 db ?? 11101100 (0xec) -80 db 11101101 (0xed) hard channel mute ?? 11111111 (0xff) hard channel mute
docid016861 rev 7 49/92 sta369bws register description 92 7.3 audio preset registers (addr 0x0b and 0x0c) 7.3.1 audio preset register 1 (addr 0x0b) using amgc[3:0] bits, attack and release thresholds and rates are automatically configured to properly fit application specific configurations. amgc[3:2] is defined in eq coefficients and drc configuration register (addr 0x31) on page 68 . the amgc[1:0] bits behave in two different ways depending on the value of amgc[3:2]. when this value is 00 then bits amgc[1:0] are defined below in table 54 . 7.3.2 audio preset register 2 (addr 0x0c) am interference frequency switching d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved amgc[1] amgc[0] reserved reserved reserved reserved 10000000 table 54. audio preset gain compression/limiters selection for amgc[3:2] = 00 amgc[1:0] mode 00 user programmable gc 01 ac no clipping 2.1 10 ac limited clipping (10%) 2.1 11 drc night-time listening mode 2.1 d7 d6 d5 d4 d3 d2 d1 d0 xo3 xo2 xo1 xo0 amam2 amam1 amam0 amame 00000000 table 55. am interference frequency switching bits bit r/w rst name description 0 r/w 0 amame audio preset am enable 0: switching frequency determined by pwms setting 1: switching frequency determined by amam settings table 56. audio preset am switching frequency selection amam[2:0] 48 khz/96 khz input fs 44.1 khz/88.2 khz input fs 000 0.535 mhz - 0.720 mhz 0.535 mhz - 0.670 mhz 001 0.721 mhz - 0.900 mhz 0.671 mhz - 0.800 mhz 010 0.901 mhz - 1.100 mhz 0.801 mhz - 1.000 mhz 011 1.101 mhz - 1.300 mhz 1.001 mhz - 1.180 mhz 100 1.301 mhz - 1.480 mhz 1.181 mhz - 1.340 mhz
register description sta369bws 50/92 docid016861 rev 7 bass management crossover 101 1.481 mhz - 1.600 mhz 1.341 mhz - 1.500 mhz 110 1.601 mhz - 1.700 mhz 1.501 mhz - 1.700 mhz table 57. bass management crossover bit r/w rst name description 4 r/w 0 xo0 selects the bass-management crossover frequency. a 1st-order hign-pass filter (channels 1 and 2) or a 2nd-order low-pass filter (channel 3) at the selected frequency is performed. 5 r/w 0 xo1 6 r/w 0 xo2 7 r/w 0 xo3 table 58. bass management crossover frequency xo[3:0] crossover frequency 0000 user-defined ( section 7.7.8 on page 61 ) 0001 80 hz 0010 100 hz 0011 120 hz 0100 140 hz 0101 160 hz 0110 180 hz 0111 200 hz 1000 220 hz 1001 240 hz 1010 260 hz 1011 280 hz 1100 300 hz 1101 320 hz 1110 340 hz 1111 360 hz table 56. audio preset am switching frequency selection (continued) amam[2:0] 48 khz/96 khz input fs 44.1 khz/88.2 khz input fs
docid016861 rev 7 51/92 sta369bws register description 92 7.4 channel configuration registers (addr 0x0e - 0x10) tone control bypass tone control (bass/treble) can be bypassed on a per channel basis for channels 1 and 2. eq bypass eq control can be bypassed on a per channel basis for channels 1 and 2. if eq control is bypassed on a given channel the prescale and all filters (high-pass, biquads, de-emphasis, bass, treble in any combination) are bypassed for that channel. volume bypass each channel contains an individual channel volume bypass. if a particular channel has volume bypassed via the cxvbp = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting has no effect on that channel. d7 d6 d5 d4 d3 d2 d1 d0 c1om1 c1om0 c1ls1 c1ls0 c1bo c1vpb c1eqbp c1tcb 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2om1 c2om0 c2ls1 c2ls0 c2bo c2vpb c2eqbp c2tcb 01000000 d7 d6 d5 d4 d3 d2 d1 d0 c3om1 c3om0 c3ls1 c3ls0 c3bo c3vpb reserved reserved 10000000 table 59. tone control bypass cxtcb mode 0 perform tone control on channel x - normal operation 1 bypass tone control on channel x table 60. eq bypass cxeqbp mode 0 perform eq on channel x - normal operation 1 bypass eq on channel x table 61. volume bypass register cxvbp mode 0 normal volume operations 1 volume is by-passed
register description sta369bws 52/92 docid016861 rev 7 binary output enable registers each individual channel output can be set to output a binary pwm stream. in this mode output a of a channel is considered the positive output and output b is negative inverse. limiter select limiter selection can be made on a per-channel basis according to the channel limiter select bits. cxls bits are not considered in case of dual band drc ( section 7.13.1 ), eq drc ( section 7.13.2 ) or gdrc ( section 7.21 ) usage. . output mapping output mapping can be performed on a per channel basis according to the cxom channel output mapping bits. each input into the output configuration engine can receive data from any of the three processing channel outputs. . table 62. binary output enable registers cxbo mode 0 ffx output operation 1 binary output table 63. channel limiter mapping as a function of cxls bits cxls[1:0] channel limiter mapping 00 channel has limiting disabled 01 channel is mapped to limiter #1 10 channel is mapped to limiter #2 table 64. channel output mapping as a function of cxom bits cxom[1:0] channel x output source from 00 channel1 01 channel 2 10 channel 3
docid016861 rev 7 53/92 sta369bws register description 92 7.5 tone control register (addr 0x11) tone control 7.6 dynamic control registers (addr 0x12 - 0x15) 7.6.1 limiter 1 attack/release rate (addr 0x12) 7.6.2 limiter 1 attack/release threshold (addr 0x13) d7 d6 d5 d4 d3 d2 d1 d0 ttc3 ttc2 ttc1 ttc0 btc3 btc2 btc1 btc0 01110111 table 65. tone control boost/cut as a function of btc and ttc bits btc[3:0]/ttc[3:0] boost/cut 0000 -12 db 0001 -12 db 0010 -10 db ?? 0101 -4 db 0110 -2 db 0111 0 db 1000 +2 db 1001 +4 db ?? 1100 +10 db 1101 +12 db 1110 +12 db 1111 +12 db d7 d6 d5 d4 d3 d2 d1 d0 l1a3 l1a2 l1a1 l1a0 l1r3 l1r2 l1r1 l1r0 01101010 d7 d6 d5 d4 d3 d2 d1 d0 l1at3 l1at2 l1at1 l1at0 l1rt3 l1rt2 l1rt1 l1rt0 01101001
register description sta369bws 54/92 docid016861 rev 7 7.6.3 limiter 2 attack/release rate (addr 0x14) 7.6.4 limiter 2 attack/release threshold (addr 0x15) 7.6.5 description the sta369bws includes two independent limiter blocks. the purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode or to actively reduce the dynamic range for a better listening environment such as a night-time listening mode which is often needed for dvds. the two modes are selected via the drc bit in configuration register e (addr 0x04) on page 35 . each channel can be mapped to either limiter or not mapped, meaning that channel will clip when 0 dbfs is exceeded. each limiter looks at the present value of each channel that is mapped to it, selects the maximum absolute value of all these channels, performs the limiting algorithm on that value, and then if needed adjusts the gain of the mapped channels in unison. figure 19. basic limiter and volume flow diagram the limiter attack thresholds are determined by the lxat registers if eathx[7] bits are set to 0 else the thresholds are determined by eathx[6:0]. it is recommended in anti-clipping mode to set this to 0 dbfs, which corresponds to the maximum unclipped output power of a ffx amplifier. since gain can be added digitally within the sta369bws it is possible to exceed 0 dbfs or any other lxat setting, when this occurs, the limiter, when active, automatically starts reducing the gain. the rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. gain reduction occurs on a peak-detect algorithm. setting eathx[7] bits to 1 selects the anti-clipping mode. the limiter release thresholds are determined by the lxrt registers if erthx[7] bits are set to 0 else the thresholds are determined by erthx[6:0]. settings to 1 erthx[7] bits the anti-clipping mode is selected automatically. the release of limiter, when the gain is again increased, is dependent on a rms-detect algorithm. the output of the volume/limiter block is passed through a rms filter. the output of this filter is compared to the release threshold, determined by the release threshold register. when the rms filter output falls below the d7 d6 d5 d4 d3 d2 d1 d0 l2a3 l2a2 l2a1 l2a0 l2r3 l2r2 l2r1 l2r0 01101010 d7 d6 d5 d4 d3 d2 d1 d0 l2at3 l2at2 l2at1 l2at0 l2rt3 l2rt2 l2rt1 l2rt0 01101001
docid016861 rev 7 55/92 sta369bws register description 92 release threshold, the gain is again increased at a rate dependent upon the release rate register. the gain can never be increased past its set value and, therefore, the release only occurs if the limiter has already reduced the gain. the release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as over limiting can reduce the dynamic range to virtually zero and cause program material to sound ?lifeless?. in ac mode, the attack and release thresholds are set relative to full-scale. in drc mode, the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold. table 66. limiter attack rate vs lxa bits lxa[3:0] attack rate db/ms 0000 3.1584 fast slow 0001 2.7072 0010 2.2560 0011 1.8048 0100 1.3536 0101 0.9024 0110 0.4512 0111 0.2256 1000 0.1504 1001 0.1123 1010 0.0902 1011 0.0752 1100 0.0645 1101 0.0564 1110 0.0501 1111 0.0451
register description sta369bws 56/92 docid016861 rev 7 anti-clipping mode table 67. limiter release rate vs lxr bits lxr[3:0] release rate db/ms 0000 0.5116 fast slow 0001 0.1370 0010 0.0744 0011 0.0499 0100 0.0360 0101 0.0299 0110 0.0264 0111 0.0208 1000 0.0198 1001 0.0172 1010 0.0147 1011 0.0137 1100 0.0134 1101 0.0117 1110 0.0110 1111 0.0104 table 68. limiter attack threshold vs lxat bits (ac mode) lxat[3:0] ac (db relative to fs) 0000 -12 0001 -10 0010 -8 0011 -6 0100 -4 0101 -2 0110 0 0111 +2 1000 +3 1001 +4 1010 +5 1011 +6 1100 +7 1101 +8
docid016861 rev 7 57/92 sta369bws register description 92 dynamic range compression mode 1110 +9 1111 +10 table 69. limiter release threshold vs lxrt bits (ac mode) lxrt[3:0] ac (db relative to fs) 0000 - ? 0001 -29 0010 -20 0011 -16 0100 -14 0101 -12 0110 -10 0111 -8 1000 -7 1001 -6 1010 -5 1011 -4 1100 -3 1101 -2 1110 -1 1111 -0 table 70. limiter attack threshold vs lxat bits (drc mode) lxat[3:0] drc (db relative to volume) 0000 -31 0001 -29 0010 -27 0011 -25 0100 -23 0101 -21 0110 -19 0111 -17 1000 -16 table 68. limiter attack threshold vs lxat bits (ac mode) (continued) lxat[3:0] ac (db relative to fs)
register description sta369bws 58/92 docid016861 rev 7 7.6.6 limiter 1 extended attack threshold (addr 0x32) the extended attack threshold value is determined as follows: attack threshold = -12 + eath1 / 4 1001 -15 1010 -14 1011 -13 1100 -12 1101 -10 1110 -7 1111 -4 table 71. limiter release threshold vs lxrt bits (drc mode) lxrt[3:0] drc (db relative to volume + lxat) 0000 - ? 0001 -38 0010 -36 0011 -33 0100 -31 0101 -30 0110 -28 0111 -26 1000 -24 1001 -22 1010 -20 1011 -18 1100 -15 1101 -12 1110 -9 1111 -6 table 70. limiter attack threshold vs lxat bits (drc mode) (continued) lxat[3:0] drc (db relative to volume) d7 d6 d5 d4 d3 d2 d1 d0 eathen1 eath1[6] eath1[5] eath1[4] eath1[3] eath1[2] eath1[1] eath1[0] 00110000
docid016861 rev 7 59/92 sta369bws register description 92 7.6.7 limiter 1 extended release threshold (addr 0x33) the extended release threshold value is determined as follows: release threshold = -12 + erth1 / 4 7.6.8 limiter 2 extended attack threshold (addr 0x34) the extended attack threshold value is determined as follows: attack threshold = -12 + eath2 / 4 7.6.9 limiter 2 extended release threshold (addr 0x35) the extended release threshold value is determined as follows: release threshold = -12 + erth2 / 4 note: attack/release threshold step is 0.125 db in the range -12 db and 0 db. 7.7 user-defined coefficient control registers (addr 0x16 - 0x26) 7.7.1 coefficient address register (addr 0x16) 7.7.2 coefficient b1 data register bits (addr 0x17 - 0x19) d7 d6 d5 d4 d3 d2 d1 d0 erthen1 erth1[6] erth1[5] erth1[4] erth1[3] erth1[2] erth1[1] erth1[0] 00110000 d7 d6 d5 d4 d3 d2 d1 d0 eathen2 eath2[6] eath2[5] eath2[4] eath2[3] eath2[2] eath2[1] eath2[0] 00110000 d7 d6 d5 d4 d3 d2 d1 d0 erthen2 erth2[6] erth2[5] erth2[4] erth2[3] erth2[2] erth2[1] erth2[0] 00110000 d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved cfa5 cfa4 cfa3 cfa2 cfa1 cfa0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b15 c1b14 c1b13 c1b12 c1b11 c1b10 c1b9 c1b8 00000000
register description sta369bws 60/92 docid016861 rev 7 7.7.3 coefficient b2 data register bits (addr 0x1a - 0x1c) 7.7.4 coefficient a1 data register bits (addr 0x1d - 0x1f) 7.7.5 coefficient a2 data register bits (addr 0x20 - 0x22) d7 d6 d5 d4 d3 d2 d1 d0 c1b7 c1b6 c1b5 c1b4 c1b3 c1b2 c1b1 c1b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b23 c2b22 c2b21 c2b20 c2b19 c2b18 c2b17 c2b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b15 c2b14 c2b13 c2b12 c2b11 c2b10 c2b9 c2b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b7 c2b6 c2b5 c2b4 c2b3 c2b2 c2b1 c2b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c3b23 c3b22 c3b21 c3b20 c3b19 c3b18 c3b17 c3b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c3b15 c3b14 c3b13 c3b12 c3b11 c3b10 c3b9 c3b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c3b7 c3b6 c3b5 c3b4 c3b3 c3b2 c3b1 c3b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b23 c4b22 c4b21 c4b20 c4b19 c4b18 c4b17 c4b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b15 c4b14 c4b13 c4b12 c4b11 c4b10 c4b9 c4b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b7 c4b6 c4b5 c4b4 c4b3 c4b2 c4b1 c4b0 00000000
docid016861 rev 7 61/92 sta369bws register description 92 7.7.6 coefficient b0 data register bits (addr 0x23 - 0x25) 7.7.7 coefficient read/write control register (addr 0x26) 7.7.8 description coefficients for user-defined eq, mixing, scaling, and bass management are handled internally in the sta369bws via ram. access to this ram is available to the user via an i 2 c register interface. a collection of i 2 c registers are dedicated to this function. one contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from ram. three different ram banks are embedded in sta369bws. the three banks are managed in paging mode using eqcfg register bits. they can be used to store different eq settings. for speaker frequency compensation, a sampling frequency independent eq must be implemented. computing three different coefficients set for 32 khz, 44.1khz, 48 khz and downloading them into the three ram banks, it is possible to select the suitable ram block depending from the incoming frequency with a simple i 2 c write operation on register 0x31. for example, in case of different input sources (different sampling rates), the three different sets of coefficients can be downloaded once at the start up, and during the normal play it is possible to switch among the three ram blocks allowing a faster operation, without any additional download from the microcontroller. to write the coefficients in a particular ram bank, this bank must be selected first writing bit 0 and bit 1 in register 0x31. then the write procedure below can be used. note that as soon as a ram bank is selected, the eq settings are automatically switched to the coefficients stored in the active ram block. note: the read write operation on ram coefficients works only if rlcki (pin29) is switching and stable (ref. table 8 , tlrjt timing) and pll must be locked (ref bit d7 reg 0x2d). d7 d6 d5 d4 d3 d2 d1 d0 c5b23 c5b22 c5b21 c5b20 c5b19 c5b18 c5b17 c5b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b15 c5b14 c5b13 c5b12 c5b11 c5b10 c5b9 c5b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b7 c5b6 c5b5 c5b4 c5b3 c5b2 c5b1 c5b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 reserved ra r1 wa w1 0 0000
register description sta369bws 62/92 docid016861 rev 7 reading a coefficient from ram 1. select the ram block with register 0x31 bit1, bit0. 2. write 6-bits of address to i 2 c register 0x16. 3. write 1 to r1 bit in i 2 c address 0x26. 4. read top 8-bits of coefficient in i 2 c address 0x17. 5. read middle 8-bits of coefficient in i 2 c address 0x18. 6. read bottom 8-bits of coefficient in i 2 c address 0x19. reading a set of coefficients from ram 1. select the ram block with register 0x31 bit1, bit0. 2. write 6-bits of address to i 2 c register 0x16. 3. write 1 to ra bit in i 2 c address 0x26. 4. read top 8-bits of coefficient in i 2 c address 0x17. 5. read middle 8-bits of coefficient in i 2 c address 0x18. 6. read bottom 8-bits of coefficient in i 2 c address 0x19. 7. read top 8-bits of coefficient b2 in i 2 c address 0x1a. 8. read middle 8-bits of coefficient b2 in i 2 c address 0x1b. 9. read bottom 8-bits of coefficient b2 in i 2 c address 0x1c. 10. read top 8-bits of coefficient a1 in i 2 c address 0x1d. 11. read middle 8-bits of coefficient a1 in i 2 c address 0x1e. 12. read bottom 8-bits of coefficient a1 in i 2 c address 0x1f. 13. read top 8-bits of coefficient a2 in i 2 c address 0x20. 14. read middle 8-bits of coefficient a2 in i 2 c address 0x21. 15. read bottom 8-bits of coefficient a2 in i 2 c address 0x22. 16. read top 8-bits of coefficient b0 in i 2 c address 0x23. 17. read middle 8-bits of coefficient b0 in i 2 c address 0x24. 18. read bottom 8-bits of coefficient b0 in i 2 c address 0x25. writing a single coefficient to ram 1. select the ram block with register 0x31 bit1, bit0. 2. write 6-bits of address to i 2 c register 0x16. 3. write top 8-bits of coefficient in i 2 c address 0x17. 4. write middle 8-bits of coefficient in i 2 c address 0x18. 5. write bottom 8-bits of coefficient in i 2 c address 0x19. 6. write 1 to w1 bit in i 2 c address 0x26.
docid016861 rev 7 63/92 sta369bws register description 92 writing a set of coefficients to ram 1. select the ram block with register 0x31 bit1, bit0. 2. write 6-bits of starting address to i 2 c register 0x16. 3. write top 8-bits of coefficient b1 in i 2 c address 0x17. 4. write middle 8-bits of coefficient b1 in i 2 c address 0x18. 5. write bottom 8-bits of coefficient b1 in i 2 c address 0x19. 6. write top 8-bits of coefficient b2 in i 2 c address 0x1a. 7. write middle 8-bits of coefficient b2 in i 2 c address 0x1b. 8. write bottom 8-bits of coefficient b2 in i 2 c address 0x1c. 9. write top 8-bits of coefficient a1 in i 2 c address 0x1d. 10. write middle 8-bits of coefficient a1 in i 2 c address 0x1e. 11. write bottom 8-bits of coefficient a1 in i 2 c address 0x1f. 12. write top 8-bits of coefficient a2 in i 2 c address 0x20. 13. write middle 8-bits of coefficient a2 in i 2 c address 0x21. 14. write bottom 8-bits of coefficient a2 in i 2 c address 0x22. 15. write top 8-bits of coefficient b0 in i 2 c address 0x23. 16. write middle 8-bits of coefficient b0 in i 2 c address 0x24. 17. write bottom 8-bits of coefficient b0 in i 2 c address 0x25. 18. write 1 to wa bit in i 2 c address 0x26. the mechanism for writing a set of coefficients to ram provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects. when using this technique, the 6-bit address specifies the address of the biquad b1 coefficient (for example, 0, 5, 10, 20, 35 decimal), and the sta369bws generates the ram addresses as offsets from this base value to write the complete set of coefficient data. table 72. ram block for biquads, mixing, scaling, bass management index (decimal) index (hex) description coefficient default 0 0x00 channel 1 - biquad 1 c1h10(b1/2) 0x000000 1 0x01 c1h11(b2) 0x000000 2 0x02 c1h12(a1/2) 0x000000 3 0x03 c1h13(a2) 0x000000 4 0x04 c1h14(b0/2) 0x400000 5 0x05 channel 1 - biquad 2 c1h20 0x000000 ?? ? ? ? 19 0x13 channel 1 - biquad 4 c1h44 0x400000 20 0x14 channel 2 - biquad 1 c2h10 0x000000 21 0x15 c2h11 0x000000 ?? ? ? ? 39 0x27 channel 2 - biquad 4 c2h44 0x400000
register description sta369bws 64/92 docid016861 rev 7 user-defined eq the sta369bws can be programmed for four eq filters (biquads) per each of the two input channels. the biquads use the following equation: y[n] = 2 * (b 0 / 2) * x[n] + 2 * (b 1 / 2) * x[n-1] + b 2 * x[n-2] - 2 * (a 1 / 2) * y[n-1] - a 2 * y[n-2] = b 0 * x[n] + b 1 * x[n-1] + b 2 * x[n-2] - a 1 * y[n-1] - a 2 * y[n-2] where y[n] represents the output and x[n] represents the input. multipliers are 24-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7fffff (0.9999998808). 40 0x28 channel 1/2 - biquad 5 or 8 for xo = 000 high-pass 2 nd order filter for xo ?? 000 c12h0(b1/2) 0x000000 41 0x29 c12h1(b2) 0x000000 42 0x2a c12h2(a1/2) 0x000000 43 0x2b c12h3(a2) 0x000000 44 0x2c c12h4(b0/2) 0x400000 45 0x2d channel 3 - biquad for xo = 000 low-pass 2 nd order filter for xo ?? 000 c3h0(b1/2) 0x000000 46 0x2e c3h1(b2) 0x000000 47 0x2f c3h2(a1/2) 0x000000 48 0x30 c3h3(a2) 0x000000 49 0x31 c3h4(b0/2) 0x400000 50 0x32 channel 1 - prescale c1pres 0x7fffff 51 0x33 channel 2 - prescale c2pres 0x7fffff 52 0x34 channel 1 - postscale c1psts 0x7fffff 53 0x35 channel 2 - postscale c2psts 0x7fffff 54 0x36 channel 3 - postscale c3psts 0x7fffff 55 0x37 twarn/oc - limit twocl 0x5a9df7 56 0x38 channel 1 - mix 1 c1mx1 0x7fffff 57 0x39 channel 1 - mix 2 c1mx2 0x000000 58 0x3a channel 2 - mix 1 c2mx1 0x000000 59 0x3b channel 2 - mix 2 c2mx2 0x7fffff 60 0x3c channel 3 - mix 1 c3mx1 0x400000 61 0x3d channel 3 - mix 2 c3mx2 0x400000 62 0x3e unused 63 0x3f unused table 72. ram block for biquads, mixing, scaling, bass management (continued) index (decimal) index (hex) description coefficient default
docid016861 rev 7 65/92 sta369bws register description 92 coefficients stored in the user defined coefficient ram are referenced in the following manner: cxhy0 = b 1 / 2 cxhy1 = b 2 cxhy2 = -a 1 / 2 cxhy3 = -a 2 cxhy4 = b 0 / 2 where x represents the channel and the y the biquad number. for example, c2h41 is the b 2 coefficient in the fourth biquad for channel 2. crossover and biquad #8 additionally, the sta369bws can be programmed for a high-pass filter (processing channels 1 and 2) and a low-pass filter (processing channel 3) to be used for bass management crossover when the xo setting is 000 (user-defined). both of these filters when defined by the user (rather than using the preset crossover filters) are second order filters that use the biquad equation given above. they are loaded into the c12h0-4 and c3hy0-4 areas of ram noted in table 72 , addresses 0x28 to 0x31. by default, all user-defined filters are pass-through where all coefficients are set to 0, except the b 0 /2 coefficient which is set to 0x400000 (representing 0.5) prescale the sta369bws provides a multiplication for each input channel for the purpose of scaling the input prior to eq. this pre-eq scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7fffff = 0.9999998808. the scale factor for this multiplier is loaded into ram. all channels can use the channel-1 prescale factor by setting the biquad link bit. by default, all prescale factors (ram addresses 0x32 to 0x33) are set to 0x7fffff. postscale the sta369bws provides one additional multiplication after the last interpolation stage and the distortion compensation on each channel. this postscaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7fffff = 0.9999998808. the scale factor for this multiplier is loaded into ram. this postscale factor can be used in conjunction with an adc equipped micro-controller to perform power-supply error correction. all channels can use the channel-1 postscale factor by setting the postscale link bit. by default, all postscale factors (ram addresses 0x34 to 0x36) are set to 0x7fffff. when line output is being used, channel-3 postscale affects both channels 3 and 4. thermal warning and overcurrent adjustment (twocl) the sta369bws provides a simple mechanism for reacting to overcurrent or thermal warning detection in the power block. when the warning occurs, the twocl value is used to provide output attenuation clipping on all channels. the amount of attenuation to be applied in this situation can be adjusted by modifying the overcurrent and thermal warning limiting value (ram addr 0x37). by default, the overcurrent postscale adjustment factor is set to 0x5a9df7 (that is, -3 db). once the limiting is applied it remains until the device is either reset or according to the twrb and ocrb settings.
register description sta369bws 66/92 docid016861 rev 7 7.8 variable max power correction registers (addr 0x27 - 0x28) mpcc bits determine the 16 msbs of the mpc compensation coefficient. this coefficient is used in place of the default coefficient when mpcv = 1. 7.9 distortion compensation registers (addr 0x29 - 0x2a) dcc bits determine the 16 msbs of the distortion compensation coefficient. this coefficient is used in place of the default coefficient when dccv = 1. 7.10 fault detect recovery constant registers (addr 0x2b - 0x2c) fdrc bits specify the 16-bit fault detect recovery time delay. when fault is asserted, the tristate output is immediately asserted low and held low for the time period specified by this constant. a constant value of 0x0001 in this register is approximately 0.083 ms. the default value of 0x000c gives approximately 0.1 ms. note: 0x0000 is a reserved value for these registers. d7 d6 d5 d4 d3 d2 d1 d0 mpcc15 mpcc14 mpcc13 mpcc12 mpcc11 mpcc10 mpcc9 mpcc8 00011010 d7 d6 d5 d4 d3 d2 d1 d0 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 11000000 d7 d6 d5 d4 d3 d2 d1 d0 dcc15 dcc14 dcc13 dcc12 dcc11 dcc10 dcc9 dcc8 11110011 d7 d6 d5 d4 d3 d2 d1 d0 dcc7 dcc6 dcc5 dcc4 dcc3 dcc2 dcc1 dcc0 00110011 d7 d6 d5 d4 d3 d2 d1 d0 fdrc15 fdrc14 fdrc13 fdrc12 fdrc11 fdrc10 fdrc9 fdrc8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 fdrc7 fdrc6 fdrc5 fdrc4 fdrc3 fdrc2 fdrc1 fdrc0 00001100
docid016861 rev 7 67/92 sta369bws register description 92 7.11 device status register (addr 0x2d) this read-only register provides fault and thermal-warning status information from the power control block. logic value 1 for faults or warning means normal state. logic 0 means a fault or warning detected on power bridge. the pllul = 1 means that the pll is not locked. d7 d6 d5 d4 d3 d2 d1 d0 pllul fault uvfault reserved ocfault ocwarn tfault twarn table 73. status register bits bit r/w rst name description 7 r - pllul 0: pll locked 1: pll not locked 6 r - fault 0: fault detected on power bridge 1: normal operation 5 r - uvfault 0: vccxx internally detected < undervoltage threshold 4 r - reserved - 3 r - ocfault 0: overcurrent fault detected 2 r - ocwarn 0: overcurrent warning 1 r - tfault 0: thermal fault, junction temperature over limit 0 r - twarn 0: thermal warning, junction temperature is close to the fault condition
register description sta369bws 68/92 docid016861 rev 7 7.12 eq coefficients and drc configuration register (addr 0x31) eq ram drc / anti clipping bits amgc[3:2] change the behavior of the bits amgc[1:0] as given in table 75 below. anticlipping when amgc[3:2] = 01 ac0, ac1, ac2 settings are designed for the loudspeaker protection function, limiting at the minimum any audio artefacts introduced by typical anti-clipping / drc algorithms. more detailed information is available in the applications notes ?configurable output power rate using sta335bw? and ?sta335bws vs sta335bw?. xob this bit can be used to bypass the crossover filters. logic 1 means that the function is not active. in this case, high pass crossover filter works as a pass-through on the data path (b0 = 1, all the other coefficients at logic 0) while the low-pass filter is configured to have zero signal on channel-3 data processing (all the coefficients are at logic 0). d7 d6 d5 d4 d3 d2 d1 d0 xob reserved reserved amgc[3] amgc[2] reserved sel[1] sel[0] 00000000 table 74. eq ram select sel[1:0] eq ram bank selected 00 / 11 bank 0 activated 01 bank 1 activated 10 bank 2 activated table 75. anti clipping and drc preset amgc[3:2] anti clipping and drc preset selected 00 drc / anti-clipping behavior is described in table 54 on page 49 (default) 01 drc / anti-clipping behavior is described table 76 on page 68 10 / 11 reserved table 76. anti-clipping selection for amgc[3:2] = 01 amgc[1:0] mode 00 ac0, stereo anticlipping 0db limiter 01 ac1, stereo anticlipping +1.25 db limiter 10 ac2, stereo anticlipping +2 db limiter 11 reserved do not use
docid016861 rev 7 69/92 sta369bws register description 92 7.13 extended configuration register (addr 0x36) extended configuration register provides access to b 2 drc and biquad 5, 6 and 7. 7.13.1 dual-band drc (b 2 drc) sta369bws device provide a dual-band drc (b 2 drc) on the left and right channels data path, as depicted in figure 20 . dual-band drc is activated by setting mdrc[1:0] = 1x. figure 20. b 2 drc scheme the low frequency information (lfe) is extracted from left and right channels, removing the high frequencies using a programmable biquad filter, and then computing the difference with the original signal. limiter 1 (drc1) is then used to control left/right high frequency components amplitude while limiter 2 (drc2) is used to control the low frequency components (see chapter 7.6 ). the cut-off frequency of the high pass filters can be user defined, xo[3:0] = 0, or selected from the predefined values. drc1 and drc2 are then used to independently limit l/r high frequencies and lfe channels amplitude (see chapter 7.6 ) as well as their volume control. to be noted that, in this configuration, the dedicated channel 3 volume control can be actually acted as a bass boost enhancer as well (0.5 db/step resolution). the processed lfe channel is then recombined with the l and r channels in order to reconstruct the 2.0 output signal. sub-band decomposition the sub-band decomposition for b 2 drc can be configured specifying the cutoff frequency. the cut off frequency can be programmed in two ways, using xo bits in register 0x0c, or using ?user programmable? mode (coefficients stored in ram addresses 0x28 to 0x31). d7 d6 d5 d4 d3 d2 d1 d0 mdrc[1] mdrc[0] ps48db xar1 xar2 bq5 bq6 bq7 00000000
register description sta369bws 70/92 docid016861 rev 7 for the user programmable mode, use the formulae below to compute the high pass filters: where alpha = (1-sin( ? 0 )) / cos( ? 0 ), and ? 0 is the cut-off frequency. a first-order filter is suggested to guarantee that for every ? 0 the corresponding low-pass filter obtained as difference (as shown in figure 20 ) has a symmetric (relative to hp filter) frequency response, and the corresponding recombination after the drc has low ripple. second-order filters can be used as well, but in this case the filter shape must be carefully chosen to provide good low pass response and minimum ripple recombination. for second- order is not possible to give a closed formula to get the best coefficients, but empirical adjustment should be done. drc settings the drc blocks used by b 2 drc are the same as those described in chapter 7.6 . b 2 drc configure automatically the drc blocks in anticlipping mode. attack and release thresholds can be selected using registers 0x32, 0x33, 0x34, 0x35, while attack and release rates are configured by registers 0x12 and 0x14. band downmixing the low-frequency band is down-mixed to the left and right channels at the b 2 drc output. channel volume can be used to weight the bands recombination to fine tune the overall frequency response. 7.13.2 eq drc mode setting mdrc = 01, it is possible to add a programmable biquad (the xo biquad at ram addresses 0x28 to 0x2c is used for this purpose) to the limiter/compressor measure path (side chain). using eqdrc the peak detector input can be shaped in frequency using the programmable biquad. for example, if a bass boost of +2 db is applied (using a low-shelf filter, for instance), the effect is that the eqdrc out will limit bass frequencies to 2 db below the selected attack threshold. generally speaking, if the biquad boosts frequency f with an amount of x db, the level of a compressed sine wave at the output is th - x, where th is the selected attack threshold. note: eqdrc works only if the biquad frequency response magnitude is >= 0 db for every frequency. b0 = (1 + alpha) / 2 a0 = 1 b1 = -(1 + alpha) / 2 a1 = -alpha b2 = 0 a2 = 0
docid016861 rev 7 71/92 sta369bws register description 92 figure 21. eqdrc scheme extended postscale range postscale is an attenuation by default. when ps48db is set to 1, a 48-db offset is applied to the configured word, so postscale can act as a gain too. extended attack rate the attack rate shown in table 66 can be extended to provide up to 8 db/ms attack rate on both limiters. extended biquad selector de-emphasis filter as well as bass and treble controls can be configured as user defined filters when equalization coefficients link is activated (bql = 1) and the corresponding bqx bit is set to 1. table 77. bit ps48db description ps48db mode 0 postscale value is applied as defined in coefficient ram 1 postscale value is applied with +48-db offset with respect to the coefficient ram value table 78. bit xar1 description xar1 mode 0 limiter1 attack rate is configured using table 66 1 limiter1 attack rate is 8 db/ms table 79. bit xar2 description xar2 mode 0 limiter2 attack rate is configured using table 66 1 limiter2 attack rate is 8 db/ms
register description sta369bws 72/92 docid016861 rev 7 when filters from 5th to 7th are configured as user-programmable, the corresponding coefficients are stored respectively in addresses 0x14-0x18 (bq5), 0x19-0x1d (bq6) and 0x1e-0x22 (bq7) as in table 72 . note: bqx bits are ignored if bql = 0 or if demp = 1 (relevant for bq5) or cxtcb = 1 (relevant for bq6 and bq7). 7.14 soft volume configuration registers (addr 0x37 - 0x38) soft volume update has a fixed rate by default. using register 0x37 and 0x38 it is possible to override the default behavior allowing different volume change rates. it is also possible to independently define the fade-in (volume is increased) and fade-out (volume is decreased) rates according to the desired behavior. table 80. bit bq5 description bq5 mode 0 preset de-emphasis filter selected 1 user defined biquad 5 coefficients are selected table 81. bit bq6 description bq6 mode 0 preset bass filter selected as per table 65 1 user defined biquad 6 coefficients are selected table 82. bit bq7 description bq7 mode 0 preset treble filter selected as per table 65 1 user defined biquad 7 coefficients are selected d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved svupe svup[4] svup[3] svup[2] svup[1] svup[0] 00000000 d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved svdwe svdw4] svdw[3] svdw[2] svdw[1] svdw[0] 00000000 table 83. bit svupe description svupe mode 0 when volume is increased, use the default rate 1 when volume is increased, use the rates defined by svup[4:0]
docid016861 rev 7 73/92 sta369bws register description 92 when svupe = 1 the fade-in rate is defined by the svup[4:0] bits according to the formula: fade-in rate = 48 / (n + 1) db/ms where n is the svup[4:0] value. when svdwe = 1 the fade-out rate is defined by the svdw[4:0] bits according to the formula: fade-in rate = 48 / (n + 1) db/ms where n is the svdw[4:0] value. note: for fade-out rates greater than 6 db/ms it is suggested to disable cpwmen bit ( miscellaneous registers (addr 0x4b, 0x4c) on page 78 ) and zce bit ( configuration register e (addr 0x04) on page 35 ) in order to avoid any audible pop noise. 7.15 drc rms filter coefficients (addr 0x39-0x3e) signal level detection in drc algorithm is computed using the following formula: y(t) = c0 * abs(x(t)) + c1 * y(t-1) where x(t) represents the audio signal applied to the limiter, and y(t) the measured level. table 84. bit svdwe description svdwe mode 0 when volume is decreased, use the default rate 1 when volume is decreased, use the rates defined by svdw[4:0] d7 d6 d5 d4 d3 d2 d1 d0 r_c0[23] r_c0[22] r_c0[21] r_c0[20] r_c0[19] r_c0[18] r_c0[17] r_c0[16] 00000001 d7 d6 d5 d4 d3 d2 d1 d0 r_c0[15] r_c0[14] r_c0[13] r_c0[12] r_c0[11] r_c0[10] r_c0[9] r_c0[8] 11101110 d7 d6 d5 d4 d3 d2 d1 d0 r_c0[7] r_c0[6] r_c0[5] r_c0[4] r_c0[3] r_c0[2] r_c0[1] r_c0[0] 11111111 d7 d6 d5 d4 d3 d2 d1 d0 r_c1[23] r_c1[22] r_c1[21] r_c1[20] r_c1[19] r_c1[18] r_c1[17] r_c1[16] 01111110 d7 d6 d5 d4 d3 d2 d1 d0 r_c1[15] r_c1[14] r_c1[13] r_c1[12] r_c1[11] r_c1[10] r_c1[9] r_c1[8] 11000000 d7 d6 d5 d4 d3 d2 d1 d0 r_c1[7] r_c1[6] r_c1[5] r_c1[4] r_c1[3] r_c1[2] r_c1[1] r_c1[0] 00100110
register description sta369bws 74/92 docid016861 rev 7 7.16 extra volume resolution configuration registers (addr 0x3f) extra volume resolution allows fine volume tuning in steps of 0.125 db. the feature is enabled when vresen = 1, as depicted in figure 22 . the overall channel volume in this case is cxvol + cxvr (in db). figure 22. extra resolution volume scheme if vresen = 0 the channel volume is defined only by cxvol registers. fine tuning steps can be set according to the following table for channels 1, 2, 3: two different behaviors can be configured by vrestg bit. if vrestg = 0 the cxvr contribution is applied immediately after the corresponding i 2 c bits are written. if vrestg = 1 the cxvr bits are effective on channel volume only after the corresponding cxvol register or master volume register is written (even to the previous values). d7 d6 d5 d4 d3 d2 d1 d0 vresen vrestg c3vr[1] c3vr[0] c2vr[1] c2vr[0] c1vr[1] c1vr[0] 00000000 table 85. bits cxvr description cxvr[1:0] mode 00 0 db 01 -0.125 db 10 -0.25 db 11 -0.375 db
docid016861 rev 7 75/92 sta369bws register description 92 7.17 short-circuit protection mode registers shok (addr 0x46) the following power-bridge pins short-circuit protection are implemented in root part number 1: ? outxx vs gndx ? outxx vs vccx the protection is enabled when register misc2 (address 0x4c) bit shen is set to 1. the protection checks the short circuit when eapd bit is toggled from 0 to 1 (that is, the power bridge is switched on), and only if it passes the test (no short) will the power bridge leave the 3-state condition. register 0x46 (read-only register) gives more information about the detected short type. gndxx equal to 0 means that outxx is shorted to ground, while the same value on vccxx means that outxx is shorted to v cc . to be noted that once the check is performed, and the tristate released, the short-circuit protection is not active again until the next eapd 0 -> 1 toggling. it means that shorts happening during normal operation are not detected. the content of register 0x46 is meaningful only after eapd bit is set to 1 at least once. the short-circuit protection implemented is effective only in btl configuration, and it must not be activated (that is, shen must be 0) in single-ended applications. table 86. bits vresen and vrestg description vresen vrestg mode 0 0 extra volume resolution disabled 0 1 extra volume resolution disabled 1 0 fine volume tuning enabled and applied immediately 11 fine volume tuning enabled and applied when master or channel volume is updated d7 d6 d5 d4 d3 d2 d1 d0 gnd1a gnd1b gnd2a gnd2b vcc1a vcc1b vcc2a vcc2b 11111111
register description sta369bws 76/92 docid016861 rev 7 figure 23. short-circuit detection timing diagram (no short detected) in figure 23 the short protection timing diagram is shown. the time information is expressed in clock cycles, where the clock frequency is defined as in section . the grey colour is used for shok bits to indicate that the bits keep the status of the previous eapd 0 -> 1 toggling. nb that after reset this state is meaningless until an eapd transition has occurred. ground related shok bits are updated as soon as the gnd test is completed, while vcc bits are updated after the vcc test is completed. both gnd and vcc tests are always run (if shen bit active and eapd toggled to 1), and only if both test are successful (no short) will the bridge outputs leave the 3-state (indicated in dotted lines in the figure). if one of the two tests (or both) fail, the power bridge outputs are kept in 3-state until the procedure is restarted with a new eapd toggling. in this figure eapd is bit 7 of register 0x05. 7.18 quantization error noise correction (addr 0x48) a special feature inside the digital processing block is available. in case of poles positioned at very low frequencies, biquads filters, can generate some audible quantization noise or unwanted dc level. in order to avoid such kind of effect a quantization noise shaping capability can be used. the filter structure including this special feature, relative to each biquad is shown in figure 24 . to maintain a back compatibility with all the previous sound terminal ? products the feature is not activated by default. it can be enabled independently for each biquad using i 2 c d7 d6 d5 d4 d3 d2 d1 d0 nshxen nshb7en nshb6en nshb5en nshb4en nshb3en nshb2en nshb1en 00000000
docid016861 rev 7 77/92 sta369bws register description 92 registers. d7 bit, when set, is responsible to activate this function on the crossover filter while the other bits address any specific biquads as per previous table. channels 1 and 2 share the same settings. bit d7 is effective also for channel 3 if the relative ocfg is used. figure 24. biquad filter structure with quantization-error noise shaping 7.19 extended coefficient range up to +4/-4 (addr 0x49, 0x4a) biquads from 1 to 7 have the possibility to extend the coefficient range from +1/-1 to +4/-4. this allows the realization of high shelf filters that may require a coefficients dynamic greater than 1 (absolute value). three ranges are available, +1/-1, +2/-2, +4/-4. to maintain a back compatibility with all the previous sound terminal ? products, the extended range is not activated by default. each biquad has its independent setting as per the table below: in this case the user can decide, for each filter stage, the correct coefficients range. note that for a given biquad the same range is applied to left and right (channel 1 and channel 2). crossover biquads do not have this feature and maintain the +1/-1 range unchanged. d7 d6 d5 d4 d3 d2 d1 d0 cxtb4[1] cxtb4[0] cxtb3[1] cxtb3[0] cxtb2[1] cxtb2[0] cxtb1[1] cxtb1[0] 00000000 d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved cxtb7[1] cxtb7[0] cxtb6[1] cxtb6[0] cxtb5[1] cxtb5[0] 00000000 table 87. coefficients extended range configuration cext_bx[1:0] coefficient range 00 +1/-1 01 +2/-2 10 +4/-4 11 reserved
register description sta369bws 78/92 docid016861 rev 7 7.20 miscellaneous registers (addr 0x4b, 0x4c) 7.20.1 misc1 (addr 0x4b) rate powerdown enable (rpdnen) bit in root part number 1, by default, powerdown pin and i 2 c powerdown act on mute commands to perform the fadeout. this default can be changed so that the fadeout can be started using master volume. rpdnen bit, when set, activates this feature. noise shaping on dc-cut filter enable (nshhpen) bit following what described in section 7.18 , this bit, when set, enables the noise shaping technique on dc-cut filter. channels 1 and 2 share the same settings. bridge immediate off (bridgoff) bit a fadeout procedure is started in root part number 1, once pwdn function is enabled and after 13 million clock cycles (pll internal frequency) the bridge is put in powerdown (tristate mode). there is also the possibility to change this behavior so that the power bridge is switched off immediately after pwdn pin is tied to ground, without, therefore waiting for the 13 million clock cycles. bridgoff bit, when set, activates this function. obviously, the immediate powerdown generates a pop noise at the output, hence this procedure must be used only in cases where pop noise is not relevant in the application. note that this feature works only for hardware pwdn assertion and not for a power down applied through i 2 c interface. refer to section : power down delay selector (pndlsl[2:0]) bits on page 81 when it is necessary to program a different number of clock cycles. f3x? mode activation (f3x) bits f3x? technology allows the pwm carrier to be suppressed for the auxiliary outputs. when activated, pins 17, 18, 19 and 20 are the channel outputs that can be connected as per figure figure 25 below. this circuit suppresses the pwm carrier fundamental and its harmonics by low-pass filtering the stereo signal. typical resistor and capacitor values are given for filtering the pwm signal. note: f3x mode works only with binary modulation. see section : binary output enable registers on page 52 for how to select this configuration. d7 d6 d5 d4 d3 d2 d1 d0 rpdnen nshhpen bridgoff f3xen[1] f3xen[0] cpwmen reserved boost 00000100
docid016861 rev 7 79/92 sta369bws register description 92 figure 25. external active filter with connection for f3x output the two register bits work as per the following table. channel pwm enable (cpwmen) bit this bit, when set, activates a mute output when the volume reaches a value lower than -76 dbfs. output power boosting (boost) bit the bit, when enabled, allows the maximum pwm modulation index to be increased from the default value to 100%. in this case the maximum unclipped output power can be increased accordingly. note that this feature does not add any gain to the signal, but just extends the maximum unclipped level of root part number 1. table 88. f3x bits configuration f3x[1] f3x[0] description 0 0 no f3x applied 0 1 f3x applied 1 0 reserved 1 1 reserved
register description sta369bws 80/92 docid016861 rev 7 7.20.2 misc2 (addr 0x4c) external amplifier hardware pin enable (lpdp, lpd lpde) bits pin 32 (int_line), described in table 2 , normally indicates a fault condition. however, using the following register settings, pin 32 can be reconfigured as the hardware pin enabler for an external headphone or line amplifier. in particular lpde bit, when set, activates this function. accordingly, lpd is exported to pin 32 and in case of power down assertion pin 32 is tied to lpdp. lpdp bit, when set, negates the value programmed as lpd value. this is summarized in the following table. figure 26. alternate function for int_line pin d7 d6 d5 d4 d3 d2 d1 d0 lpdp lpd lpde pndlsl[2] pndlsl[1] pndlsl[0] reserved shen 00000000 table 89. external amplifier enabler configuration bits lpdp lpd lpde pin 32 output x x 0 int_line 0010 0111 1011 1110 y n 0 lpd 0 1 lpdp 0 1 power bridge fault int_line lpde is the device in powerdown?
docid016861 rev 7 81/92 sta369bws register description 92 power down delay selector (pndlsl[2:0]) bits as per register misc1 (addr 0x4b) on page 78 , the assertion of pwdn activates a counter that, by default, after 13 million clock cycles, puts the power bridge in tristate mode independently from the fade out time. using these registers it is possible to program this counter as per the table below. short-circuit check enable (shen) bit this bit, when enabled, activates the short-circuit checks before any power bridge activation (eapd bit 0 -> 1). see section 7.17 on page 75 for more details. 7.21 global drc after b 2 drc (gdrc) bit (addr 0x4d, bit d0) gdrc bit, when set, changes the architecture configuration of the dual band drc. as a consequence, the block diagram, illustrated by the figure 20: b 2 drc scheme on page 69 , becomes that shown in figure 27 below. figure 27. global drc after b 2 drc the final effect is a global drc after the dual band drc. this architecture aims to limit the signal overshoot, generated by the different phases of the two processed data paths of the b 2 drc architecture, that could happen between the two bands. note: if gdrc is enabled, c3vr[0] and c3vr[1] must be set to 0 (default values). table 90. pndlsl bits configuration pndlsl[2] pndlsl[1] pndlsl[0] fade-out time 0 0 0 default time (13 x 10 6 pll clock cycles) 0 0 1 default time divided by 2 0 1 0 default time divided by 4 0 1 1 default time divided by 8 1 0 0 default time divided by 16 1 0 1 default time divided by 32 1 1 0 default time divided by 64 1 1 1 default time divided by 128
register description sta369bws 82/92 docid016861 rev 7 7.22 bad pwm detection registers (addr 0x4d, 0x4e, 0x4f) root part number 1 implements a detection on pwm outputs which is able to verify if the output signal has no zero crossing in a configurable time window. this check is useful to detect the dc level in the pwm outputs. the checks are performed at logic level pwm so it is implemented inside the pwm modulator logic. in the case of ternary modulation, the detection threshold is computed as: th = ((bpth * 2 + 1) / 128) * 100% if the measured pwm duty cycle is detected greater or equal to th for more than bptim pwm periods, the corresponding pwm bit is set in register 0x4e. in the case of binary modulation, there are two thresholds: th1 = ((64 + bpth) / 128) * 100% th2 = ((64 - bpth) / 128) * 100% in this case, if the measured pwm duty cycle is outside the th1 to th2 range for more than bptim pwm periods, the corresponding bit is set in register 0x4e. 7.23 coefficient ram crc protection (addr 0x60-0x6c) 7.23.1 bqchke registers (addr 0x60 - 0x62) d7 d6 d5 d4 d3 d2 d1 d0 bpth[5] bpth[4] bpth[3] bpth[2] bpth[1] bpth[0] reserved gdrc 00110010 d7 d6 d5 d4 d3 d2 d1 d0 bp4b bp4a bp3b bp3a bp2b bp2a bp1b bp1a 00000000 d7 d6 d5 d4 d3 d2 d1 d0 bptim[7] bptim[6] bptim[5] bptim[4] bptim[3] bptim[2] bptim[1] bptim[0] 00000000 d7 d6 d5 d4 d3 d2 d1 d0 bqchke[7] bqchke[6] bqchke[5] bqchke[4] bqchke[3] bqchke[2] bqchke[1] bqchke[0] 00000000 d7 d6 d5 d4 d3 d2 d1 d0 bqchke[15] bqchke[14] bqchke[13] bqchke[12] bqchke[11] bqchke[10] bqchke[9] bqchke[8] 00000000 d7 d6 d5 d4 d3 d2 d1 d0 bqchke[23] bqchke[22] bqchke[21] bqchke[20] bqchke[19] bqchke[18] bqchke[17] bqchke[16] 00000000
docid016861 rev 7 83/92 sta369bws register description 92 7.23.2 xcchke registers (addr 0x63 - 0x65) 7.23.3 bqchkr registers (addr 0x66 - 0x68) 7.23.4 xcchkr registers (addr 0x69 - 0x6b) 7.23.5 chkctrl register (addr 0x6c) d7 d6 d5 d4 d3 d2 d1 d0 xcchke[7] xcchke[6] xcchke[5] xcchke[4] xcchke[3] xcchke[2] xcchke[1] xcchke[0] 00000000 d7 d6 d5 d4 d3 d2 d1 d0 xcchke[15] xcchke[14] xcchke[13] xcchke[12] xcchke[11] xcchke[10] xcchke[9] xcchke[8] 00000000 d7 d6 d5 d4 d3 d2 d1 d0 xcchke[23] xcchke[22] xcchke[21] xcchke[20] xcchke[19] xcchke[18] xcchke[17] xcchke[16] 00000000 d7 d6 d5 d4 d3 d2 d1 d0 bqchkr[7] bqchkr[6] bqchkr[5] bqchkr[4] bqchkr[3] bqchkr[2] bqchkr[1] bqchkr[0] 00000000 d7 d6 d5 d4 d3 d2 d1 d0 bqchkr[15] bqchkr[14] bqchkr[13] bqchkr[12] bqchkr[11] bqchkr[10] bqchkr[9] bqchkr[8] 00000000 d7 d6 d5 d4 d3 d2 d1 d0 bqchkr[23] bqchkr[22] bqchkr[21] bqchkr[20] bqchkr[19] bqchkr[18] bqchkr[17] bqchkr[16] 00000000 d7 d6 d5 d4 d3 d2 d1 d0 xcchkr[7] xcchkr[6] xcchkr[5] xcchkr[4] xcchkr[3] xcchkr[2] xcchkr[1] xcchkr[0] 00000000 d7 d6 d5 d4 d3 d2 d1 d0 xcchkr[15] xcchkr[14] xcchkr[13] xcchkr[12] xcchkr[11] xcchkr[10] xcchkr[9] xcchkr[8] 00000000 d7 d6 d5 d4 d3 d2 d1 d0 xcchkr[23] xcchkr[22] xcchkr[21] xcchkr[20] xcchkr[19] xcchkr[18] xcchkr[17] xcchkr[16] 00000000 d7 d6 d5 d4 d3 d2 d1 d0 xcauto xcres xccmp xcgo bcauto bcres bccmp bcgo 01000100
register description sta369bws 84/92 docid016861 rev 7 7.23.6 description root part number 1 implements an automatic crc computation for the biquad and mdrc / xover coefficient memory ( table 72 ). ram memory cell contents from address 0x00 to 0x27 are bit xored to obtain bqchke checksum, while cells from 0x28 to 0x31 are xored to obtain the xcchke checksum. both checksum (24-bit wide) are exported on i 2 c registers from 0x60 to 0x65. the checksum computation starts as soon as the bcgo (for biquad ram bank) or the xcgo bits (for mdrc / xover coefficients) are set to 1. the checksum is computed at the processing sample rate if ir bits equal to 01 or 10, otherwise the checksum is computed to half processing sample rate. when bccmp or xccmp are set to 1 the relative checksum (bqchke and xcchke) is continuously compared with bqchkr and xcchkr respectively. if the checksum match with its own reference value, the respective result bits (bcres and xcres) are set to 0. the compare bits have no effect if the respective go bit is not set. in case of checksum errors (that is, the internally computed didn?t match the reference), an automatic device reset action can be activated. this function is enabled when bcauto or xcauto bits are set to ?1?. the automatic reset bits have no effect if the respective compare bits are not set. the suggested procedure for automatic reset activation is the following one: 1. download coefficients set (ram locations 0x00?0x27) 2. download externally computed biquad checksum into registers bqchkr 3. enable checksum of biquad coefficients by setting bcgo bit. checksum starts to be automatically computed by root part number 1 and its value written in registers bqchke. 4. enable checksum comparison by setting bccmp bit. internally computed checksum will start to be compared with the reference one and result will be exposed on the bcres bit. following operation will be executed on each audio frame: if (bqchke == bqchkr) { bc_res = 0; } // checksum is ok, reset the error bit else { bc_res = 1; } // checksum error detected, set the error bit 5. wait until the bcres bit goes to 0, meaning checksum result bit has started to be updated and everything is ok. time out for this operation (for example, >1 ms) indicates checksum failure, mcu will handle this event. 6. enable automatic reset of the device in case of checksum error by setting the bcauto bit. the bcres bit will then be automatically checked by sta369bws, on each audio frame, and reset event will be triggered in case of checksum mismatch. 7. periodically check bcres status. a value of 1 indicates a checksum mismatch has occurred and, therefore, the device went through a reset cycle. the previous example is intended for biquad crc bank calculations, but it can be easily extended to mdrc / xover crc computation.
sta369bws applications docid016861 rev 7 85/92 8 applications 8.1 application schematics figure 28 and figure 29 show the typical application schematics for stereo and mono configuration, respectively. special attention has to be paid to the layout of the pcb. all the decoupling capacitors have to be placed as close as possible to the device to limit spikes on all the supplies. figure 28. application circuit for 2 or 2.1-channel configuration
sta369bws applications docid016861 rev 7 86/92 figure 29. application circuit for mono btl configuration
docid016861 rev 7 87/92 sta369bws applications 92 8.2 pll filter circuit it is recommended to use the above circuit and values for the pll loop filter to achieve the best performance from the device in general applications. note that the ground of this filter circuit has to be connected to the ground of the pll without any resistive path. concerning the component values, it must be taken into account that the greater the filter bandwidth, the less is the lock time but the higher is the pll output jitter. 8.3 typical output configuration figure 30 shows the typical output configuration used for btl stereo mode. please contact stmicroelectronics for other recommended output configurations. figure 30. output configuration for stereo btl mode (r l = 8 ??
package thermal characteristics sta369bws 88/92 docid016861 rev 7 9 package thermal characteristics using a double-layer pcb the thermal resistance, junction to ambient, with 2 copper ground areas of 3 x 3 cm 2 and with 16 via holes is 24 c/w in natural air convection. the dissipated power within the device depends primarily on the supply voltage, load impedance and output modulation level. thus, the maximum estimated dissipated power for the sta369bws is: figure 31 shows the power derating curve for the powersso-36 package on pcbs with copper areas of 2 x 2 cm 2 and 3 x 3 cm 2 . figure 31. powersso-36 power derating curve 2 x 20 w @ 8 ?? , 18 v pd max is approximately 4 w 2 x 9 w + 1 x 20 w @ 4 ? , 8 ? , ? 18 v pd max is approximately 5 w sta369bws powersso-
docid016861 rev 7 89/92 sta369bws package mechanical data 92 10 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack ? is an st trademark. figure 32 shows the package outline and table 91 gives the dimensions. table 91. powersso-36 epd dimensions symbol dimensions in mm dimensions in inches min typ max min typ max a 2.15 - 2.47 0.085 - 0.097 a2 2.15 - 2.40 0.085 - 0.094 a1 0.00 - 0.10 0.00 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 d 10.10 - 10.50 0.398 - 0.413 e 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - f - 2.3 - - 0.091 - g - - 0.10 - - 0.004 h 10.10 - 10.50 0.398 - 0.413 h - - 0.40 - - 0.016 k 0 - 8 degrees 0 - 8 degrees l 0.60 - 1.00 0.024 - 0.039 m - 4.30 - - 0.169 - n - - 10 degrees - - 10 degrees o - 1.20 - - 0.047 - q - 0.80 - - 0.031 - s - 2.90 - - 0.114 - t - 3.65 - - 0.144 - u - 1.00 - - 0.039 - x 4.10 - 4.70 0.161 - 0.185 y 6.50 - 7.10 0.256 - 0.280
sta369bws package mechanical data docid016861 rev 7 90/92 figure 32. powersso-36 epd outline drawing h x 45
docid016861 rev 7 91/92 sta369bws revision history 92 11 revision history table 92. document revision history date revision changes 11-dec-2009 1 initial release. 10-feb-2010 2 removed preliminary banner - datasheet now final 01-mar-2010 3 added rth j-amb typical value to table 4 on page 13 added section 3.6: power on/off sequence on page 17 updated biquad # in figure 8 on page 20 updated section : fault detect recovery bypass on page 29 updated sv naming in table 42 on page 37 updated cxbo description in table 62 on page 52 updated biquad # for c12hx in table 72 on page 63 updated text in sections crossover and biquad #8 , prescale and section : postscale on page 65 . 04-nov-2010 4 updated figure 3: test circuit on page 16 clarified 2-db value (by prefixing ?+?) in section 7.13.2: eq drc mode on page 70 updated storage addresses for coefficients in section : extended biquad selector on page 71 25-sep-2013 5 added section 4 on page 18 modified note:: the read write operation on ram coefficients works only if rlcki (pin29) is switching and stable (ref. table 8, tlrjt timing) and pll must be locked (ref bit d7 reg 0x2d). on page 61 updated company information appearing on last page of document 05-nov-2013 6 modified i lim and i scp min. values in table 7 on page 15 22-sep-2014 7 updated section 1: description added 1 channel mono-parallel (ocfg = 11) in section 7.1.6: configuration register f (addr 0x05) updated figure 28: application circuit for 2 or 2.1 channel configuration and added figure 29: application circuit for mono btl configuration
sta369bws 92/92 docid016861 rev 7 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

▲Up To Search▲

Price & Availability of STA369BWSTR

	To Download STA369BWSTR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .